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Researchers Submit Patent Application, "Source Code Separation and Generation for Heterogeneous Central Processing Unit (CPU) Computational Devices",...

June 19, 2014



Researchers Submit Patent Application, "Source Code Separation and Generation for Heterogeneous Central Processing Unit (CPU) Computational Devices", for Approval

By a News Reporter-Staff News Editor at Computer Weekly News -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Brower, Jeffrey H. (Dallas, TX); Johnson, Christopher K. (Frisco, TX), filed on November 12, 2013, was made available online on June 5, 2014.

The patent's assignee is Signalogic.

News editors obtained the following quote from the background information supplied by the inventors: "The present disclosure generally relates to computing devices, and more particularly to processing source code.

"Source code is human-readable code that is eventually converted into something that a computer processor can understand to control input and output devices and/or to perform calculations. In an example, source code may be converted into machine language, which includes logical ones and zeros that present basic instructions for a target central processing unit (CPU) and is executed by the CPU. A compiler translates the source code into binary code that can be directly executed by the target CPU. In an example, the compiler produces 'native code' that is executed by the target CPU. The compiler may be specific to the target CPU, and native code may refer to code that is created to run directly only on the type of CPU for which the compiler is designed."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "Methods, systems, and techniques for preparing source code for compilation for, and eventual coordinated execution on, a heterogeneous plurality of target CPUs are provided.

"According to an embodiment, a method of preparing source code for compilation for, and eventual coordinated execution on, a heterogeneous plurality of target CPUs includes obtaining source code annotated to identify at least a first portion thereof suitable for execution on a first-type subset of the target CPUs. The method also includes based at least in part on a first annotation, separating the source code into first and second source code portions. The method further includes generating from the first source code portion a first source code stream to be supplied for compilation by a first compiler. The first source code stream is augmented, based on the first annotation, to include additional coordination code not present in the obtained source code. The first compiler is specific to the first-type subset of the target CPUs. The method also includes generating from the second source code portion a second source code stream to be supplied for compilation by a second compiler. The second compiler is specific to a second-type subset of the target CPUs. The target CPUs of the first- and second-type subsets have one or more different functionalities.

"In an example, the first annotation includes a statement introduced into the source code to mark at least a boundary between the first and second code portions. In another example, the first annotation notates, at least by target CPU type, the first-type subset of the target CPUs for which the augmented first source code stream is to be compiled. In another example, the first annotation notates a number or scale parameter for the first-type subset of the target CPUs for which the augmented first source code stream is to be compiled. According to an embodiment, the target CPUs of the first- and second-type subsets are of respectively different CPU types selected from the set of: one or more general purpose CPU cores; one or more vector, array, or graphics processing units (GPUs); one or more compute intensive multicore CPUs; and one or more one or more low-power CPU cores.

"In an example, the coordination code may include a prolog and an epilogue for initialization and clean-up tasks and at least one from a group including code download and initialization per CPU type, run-time data transfer, synchronization, resource management, core allocation, and monitoring code. In another example, the coordination code includes API calls to move run-time data, control, and status operands between target CPUs of the first- and second-type subsets. In another example, the coordination code includes code compilable to coordinate sequencing of run-time code concurrently executing on target CPUs of the first- and second-type subsets.

"According to an embodiment, the method further includes supplying the augmented first source code stream to the first compiler for compilation and supplying the second source code stream to the second compiler for compilation. According to an embodiment, the method further includes obtaining a first binary executable program created by the first compiler, where the first compiler compiled the augmented first source code stream into the first binary executable program; and obtaining a second binary executable program created by the second compiler, where the second compiler compiled the second source code stream into the second binary executable program. According to an embodiment, the method further includes supplying the first binary executable program for execution on the first-type subset of the target CPUs and supplying the second binary executable program for execution on the second-type subset of the target CPUs.

"In an example, the first source code stream is augmented, based on the first annotation, to include a reference to the second binary executable program. In another example, the second source code stream is augmented, based on the first annotation, to include additional coordination code not present in the obtained source code, where such coordination code may include code download and initialization per CPU type, run-time data transfer, synchronization, resource management, core allocation, and various types of monitoring, including core usage, memory usage, and thermal tracking. In another example, at least one target CPU of the first-type subset includes run-time data I/O resources allowing bypass of a virtualization layer, where the first source code portion includes input, processing, and output that is targeted to one or more run-time data I/O resources, and the coordination code includes code to support run-time data I/O.

"According to an embodiment, the method further includes based at least in part on a second annotation, separating the source code into a third source code portion. The method further includes generating from the third source code portion a third source code stream to be supplied for compilation by the first compiler, the third source code stream augmented, based on the second annotation, to include additional coordination code not present in the obtained source code, where such coordination code may include code download and initialization per CPU type, run-time data transfer, synchronization, resource management, core allocation, and various types of monitoring, including core usage, memory usage, and thermal tracking. The method further includes supplying the augmented third source code stream to the first compiler for compilation.

"According to another embodiment, a system for preparing source code for compilation for, and eventual coordinated execution on, a heterogeneous plurality of target CPUs includes an input/output interface that facilitates the retrieval of annotated source code. The annotated source code identifies at least a first portion thereof suitable for execution on a first-type subset of the target CPUs. The system also includes a source code separator that, based at least in part on a first annotation, separates the source code into first and second source code portions. The system further includes a source code stream pre-processor that generates from the second source code portion a second source code stream to be supplied for compilation by a second compiler. The source code stream pre-processor augments, based on the first annotation, the first source code stream to include additional coordination code not present in the obtained source code. The first compiler is specific to the first-type subset of the target CPUs. The second compiler is specific to a second-type subset of the target CPUs. The target CPUs of the first- and second-type subsets have one or more different functionalities.

"In an example, the target CPUs of the first- and second-type subsets are of respectively different CPU types selected from the set of: one or more general purpose CPU cores; one or more vector, array, or graphics processing units (GPUs); one or more high performance multicore CPUs; and one or more low-power CPUs. In another example, the coordination code includes API calls to move run-time data, control, and status operands between target CPUs of the first- and second-type subsets.

"According to an embodiment, the compiler compiles the augmented first source code stream to create a first binary executable program for execution on the first-type subset of the target CPUs. The first-type subset of the target CPUs may execute the first binary executable program. In an example, the target CPUs of the first- and second-type subsets reside in a common computing system. In another example, the target CPUs of the first- and second-type subsets reside in distributed computing systems. In another example, at least some of the first-type subset of the target CPUs reside in different computing systems. In another example, at least one target CPU of the first-type subset includes run-time data I/O resources allowing bypass of a virtualization layer, where the first source code portion includes input, processing, and output that is targeted to one or more run-time data I/O resources, and the coordination code includes code to support run-time data I/O.

"According to an embodiment, the source code pre-processor, based at least in part on a second annotation, separates the source code into a third source code portion. The source code stream pre-processor may generate from the third source code portion a third source code stream to be supplied for compilation by the first compiler. The source code stream pre-processor may also augment, based on the second annotation, the third source code stream to include additional coordination code not present in the obtained source code, where the source code stream pre-processor supplies the augmented third source code stream to the first compiler for compilation. The system may also include an editor that annotates the source code.

"In an example, the first source code stream includes machine-generated source code and the segmented first source code stream is rearranged, re-sequenced, and retimed to communicate with a binary executable program executing on the second compiler. In an example, the coordination code includes at least one from a group including code download and initialization per CPU type, run-time data transfer, synchronization, resource management, core allocation, and various types of monitoring such as core usage, memory usage, and thermal tracking. In another example, the compiler compiles the augmented first source code stream to create a plurality of first binary executable programs for execution on the first-type subset of the target CPUs, and the first-type subset of the target CPUs includes a multicore CPU, and each core executes a different binary executable program of the plurality of first binary executable programs.

"According to another embodiment, a non-transitory may be of dissimilar performance and power consumption, sizes, weights, and internal architectures includes a plurality of machine-readable instructions that when executed by one or more processors are adapted to cause the one or more processors to perform a method including: obtaining source code annotated to identify at least a first portion thereof suitable for execution on a first-type subset of the target CPUs; based at least in part on a first annotation, separating the source code into first and second source code portions; generating from the first source code portion a first source code stream to be supplied for compilation by a first compiler, the first source code stream augmented, based on the first annotation, to include additional coordination code not present in the obtained source code, and the first compiler specific to the first-type subset of the target CPUs; and generating from the second source code portion a second source code stream to be supplied for compilation by a second compiler, the second compiler specific to a second-type subset of the target CPUs, where the target CPUs of the first- and second-type subsets have one or more different functionalities.

BRIEF DESCRIPTION OF THE DRAWINGS

"The accompanying drawings, which form a part of the specification, illustrate embodiments of the invention and together with the description, further serve to explain the principles of the embodiments. In the drawings, like reference numbers may indicate identical or functionally similar elements. The drawing in which an element first appears is generally indicated by the left-most digit in the corresponding reference number.

"FIG. 1 is a block diagram illustrating a system for preparing source code for compilation for, and eventual coordinated execution on, a heterogeneous plurality of target CPUs, according to an embodiment.

"FIG. 2 is a flow diagram illustrating a flow for coordinated execution of prepared source code on the heterogeneous plurality of target CPUs, according to an embodiment.

"FIG. 3 illustrates an example of source code that is annotated for separation, according to an embodiment.

"FIG. 4 illustrates a relationship between FIGS. 4A and 4B. FIGS. 4A and 4B illustrate an example of an augmented source code stream, according to an embodiment.

"FIG. 5 is a block diagram illustrating binary executable programs being supplied to the heterogeneous plurality of target CPUs, according to an embodiment.

"FIG. 6 is a flow diagram illustrating a flow for preparing source code for compilation for, and eventual coordinated execution on, a heterogeneous plurality of target CPUs, according to an embodiment.

"FIG. 7 is a flow diagram illustrating a flow for processing source code streams for compilation and for eventual coordinated execution on a heterogeneous plurality of target CPUs, according to an embodiment.

"FIG. 8 is a block diagram illustrating an external data I/O path in a virtualized computer system, according to an embodiment.

"FIG. 9 is a block diagram illustrating an external data I/O path to and from an accelerator in a virtualized computer system, according to an embodiment.

"FIG. 10 is a flowchart illustrating a method of preparing source code for compilation for, and eventual coordinated execution on, a heterogeneous plurality of target CPUs, according to an embodiment.

"FIG. 11 is a block diagram of an electronic system suitable for implementing one or more embodiments of the present disclosure.

"Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows."

For additional information on this patent application, see: Brower, Jeffrey H.; Johnson, Christopher K. Source Code Separation and Generation for Heterogeneous Central Processing Unit (CPU) Computational Devices. Filed November 12, 2013 and posted June 5, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=185&p=4&f=G&l=50&d=PG01&S1=20140529.PD.&OS=PD/20140529&RS=PD/20140529

Keywords for this news article include: Signalogic.

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