News Column

Patent Issued for Storage Apparatus, Computer System, and Method for Managing Storage Apparatus

June 19, 2014



By a News Reporter-Staff News Editor at Computer Weekly News -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Nishihara, Toshiyuki (Kanagawa, JP); Date, Kazuyuki (Kanagawa, JP), filed on January 3, 2008, was published online on June 3, 2014.

The assignee for this patent, patent number 8745310, is Sony Corporation (Tokyo, JP).

Reporters obtained the following quote from the background information supplied by the inventors: "The present invention relates to a storage apparatus and a computer system including a non-volatile memory and a method for managing the storage apparatus.

"In recent years, flash memories have been attracting attention as storage media for a digital still camera, a portable computer device, or the like.

"The flash memory is a semiconductor memory that uses tunneling or hot-electron injection to cause electrons to pass through a gate insulating film to be injected into a floating gate or a trapping layer so that a threshold of a cell transistor will be changed to store data. In the flash memory, a memory cell can be formed by one transistor using a stacked gate structure, a MNOS structure, or the like, and thus inexpensive and large-capacity memory can be achieved.

"Meanwhile, the flash memory has a very slow programming speed, requiring hundreds of microseconds (.mu.s) per cell. Moreover, since overwriting of data is not allowed, an erase operation needs to be performed before programming, and this takes as long as several milliseconds. Such a problem is dealt with by parallel processing for multiple memory cells.

"A simple example of a structure of a NAND flash memory, which is a typical example of flash memory, is illustrated in FIG. 1.

"In a flash memory 1, a group 2 of cells connected to the same word line, for example, is a unit by which writing and reading are performed at a time, and is called a page. Further, a cell array 3 composed of a plurality of pages is a unit by which erasure is performed at a time, and is called a block. The entire flash memory 1 is composed of a plurality of blocks.

"Specifically, ISSCC 2002 Digest, p. 106, session 6.4, for example, describes a 1-Gb NAND flash memory with a page size of 2k bytes and an erasure block size of 128 kB. That is, in one memory array, a group of memory cells with a size of 128k bytes are erased in parallel, and the memory cells are programmed in parallel in units of 2k bytes, so that a programming transfer rate of 10 MB/s is achieved.

"In general, each page of the NAND flash has a 64-byte spare area while having a 2k-byte storage area for user data, for example.

"A system that uses the NAND flash is able to store various management data, such as parity bits, in this spare area. Writing to this spare area generally needs to be performed simultaneously with writing to the area for the user data, and these two areas are handled as a set.

"One noteworthy limitation of the flash memory is that an upper bound of the number of times erasure can be performed is specified.

"If the number of times erasure has been performed exceeds the upper bound after repeated rewriting to the same block, data storage in that block ceases to be guaranteed. The upper bound of the number of times erasure can be performed for the above NAND flash is one hundred thousand or less, for example.

"With increasing miniaturization of memory cells, variations in the threshold of cell transistors have been increasing, and the operation margin has been deteriorating, resulting in the tendency for the upper bound of the number of times of erasure to decrease further.

"Further, in recent years, there has been a tendency for the following new limitations to be placed on the NAND flash in particular, because of changes in internal structure and writing mechanism caused by the miniaturization.

"First, a new limitation has been placed on the order in which the pages in the block are written.

"Specifically, writing to the pages can be performed in a forward direction, from lower addresses to higher addresses, while writing in an opposite direction is prohibited. For example, once data is written to a certain page, writing of data to lower addresses in the same block is not permitted even when no data has been written to the lower addresses.

"Secondly, multiple writing to a page has become difficult. That is, it has become difficult to write data to the same page at two separate times. Therefore, it is becoming difficult to use various techniques formerly used for management of the flash memory, such as marking some bits in the spare area before writing data to the page, or setting a flag in the spare area after data writing."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "In recent years, the flash memory has been expected to substitute for hard disks in order to overcome the problems of hard disks, such as high power consumption, a long seek time, low shock resistance, and poor portability.

"As described above, the flash memory, however, has a disadvantage of the inability to increase speed without increasing an access unit. Moreover, since data overwriting is not allowed, rewriting may not be achieved without erasure, and a block to be erased at the time of rewriting is significantly large. An erasure unit is tens times as large as the access unit, and this is a part of the general specifications of the flash memory, in which an erasure time is long and a disturbance occurs in cells not being selected at the time of writing.

"In order to cope with such specifications of the flash memory and achieve high-speed rewriting, even of a small amount of data, a multisession storage system has been proposed.

"In such a system, rewriting is achieved by writing updated data to a free space and invalidating original data.

"More specifically, an address translation table for associating logical addresses with physical addresses on a page-by-page basis is used, and rewriting is achieved by changing the physical address of data concerned and writing the data to a free space in a storage medium.

"For example, Japanese Patent Laid-open No. Hei 8-328762 describes the details of a management method in a multisession storage system using the address translation table. FIG. 2 shows one example.

"In FIG. 2, reference numeral 10 indicates a flash memory, reference numeral 11 indicates a block, reference numeral 12 indicates a page area, reference numeral 13 indicates a page buffer, reference numeral 14 indicates an erased empty block, reference numeral 15 indicates a page area, reference numeral 16 indicates a spare area, and reference numeral 17 indicates the address translation table.

"In the address translation table 17, logical page addresses (LPAs) can be used as indexes to acquire corresponding physical page address (PPAs), which are addresses in the flash memory of corresponding pages.

"Suppose, for example, that writing to a logical page address '0x5502' is specified by a host. In this case, the address translation table is used to perform address translation on a page basis, and a physical page address '0x6B05' in the flash memory 10 is acquired. As a result, access to the corresponding page area 12 in the block 11 is carried out.

"Meanwhile, in the case where this page is updated, an appropriate free page area in the flash memory to which data can be written directly is searched for. Suppose, for example, that the top page area 15 in the erased empty block 14 corresponding to a physical block address '0xAA' is selected as an appropriate page area to which the data is to be written. In this case, data in the page area 12 is updated and written to the page area 15 via the page buffer 13. At this time, the logical page address '0x5502' is remapped to a physical address '0xAA00' of the page area 15, and a relevant field in the address translation table 17 is updated accordingly.

"The original data in the page area 12 is invalidated and allowed to remain therein for the time being.

"When the data is written to the page area 15, the corresponding logical page address '0x5502' is simultaneously written to the spare area 16. As a result, the spare area 16 can be referenced to find a correspondence between the physical page address '0xAA00' and the logical page address '0x5502'.

"According to such management, high-speed writing and rewriting to any logical address can be achieved on a page basis as long as there is a free space in the flash memory. That is, an empty block convenient for writing may be searched for, and writing may be performed in the empty block sequentially starting with the top page thereof. Since erasure is not processed during this process, the number of times of rewriting for the flash memory can be reduced significantly, resulting in a prolonged life of the flash memory.

"If data updating is performed repeatedly in such a system, resulting in accumulation of invalidated pages, a storage area of the storage will become short of free space. Therefore, a block including many invalidated pages is selected at an appropriate time, and the selected block is subjected to a recovery process.

"Specifically, effective pages in the selected block are all copied to another block before erasing the selected block, corresponding physical addresses described in the address translation table are updated accordingly, and finally the selected block is erased. These operations may be performed while the storage apparatus is in a standby state or while the system is in an idle state. This contributes to concealing the overhead from an user.

"In such a storage system, the address translation table 17 is commonly stored in a volatile RAM, such as a SRAM, in order to allow high-speed access. The address translation table 17 is backed up to the flash memory when power is turned off, and, upon power-up, is loaded again into the RAM and reconstructed.

"When an instantaneous power interruption occurs, however, the table will be lost while such a backup copy does not exist, with the result that the correspondences between the logical addresses and the physical addresses are unknown. At this time, the system attempts to reconstruct the address translation table 17, and the reconstruction of the address translation table 17 is achieved by scanning spare areas of all pages in the flash memory 10.

"That is, since the spare area of each page stores a corresponding logical page address, the correspondences between the physical page addresses and the logical page addresses throughout the entire flash memory 10 can be checked by scanning all the pages in the flash memory 10 in accordance with the physical page addresses.

"Note that, when a data update has been performed, the same logical page address is described in the spare areas of both the page in which the original data is stored and the page in which the updated data is stored. In this case, historical information (e.g., a time stamp) used for determining which data is older may be described in the spare area along with the logical page address. A page in which a logical page address that is also described in another page and which has an older writing history than the other page is described can be identified as an invalidated page, and the correspondence between the logical address and the physical address described therein can be neglected. In such a procedure, a complete reconstruction of the address translation table 17 is achieved.

"However, with the increased capacity of the flash memory, it takes an enormous amount of time to scan the spare areas of all the pages of the flash memory and perform the necessary processes. When the flash memory is 1 GB in size and is composed of 2-kB pages, for example, the number of pages is as large as 512 k. Since reading the spare area of each page needs approximately 50 microseconds, simply scanning all pages needs as long as 25.6 seconds. Moreover, it takes more than twice as long a time to reconstruct the table using limited RAM resources.

"Therefore, after the power of the storage system is instantaneously interrupted as a result of a plug being removed from a receptacle, for example, the system may not be started even nearly one minute after power-up.

"In the case of removable media, because removing the media by the user leads directly to an instantaneous power interruption, the instantaneous power interruption may occur frequently, meaning uselessness in such applications.

"An advantage of the present invention is to provide a storage apparatus, a computer system, and a method for managing the storage apparatus, which enable reconstruction of the address translation table for a short time after an instantaneous power interruption, regardless of the capacity of storage.

"According to one embodiment of the present invention, there is provided a storage apparatus including: a flash memory device as a main memory; a second memory for storing an address translation table; and a control section configured to control the flash memory device and the second memory. The flash memory device is formed of a plurality of pages, each of the pages having a spare area. Data is stored on a page-by-page basis. The control section has: a function of saving the address translation table within the second memory to the flash memory device as appropriate; a function of, when writing or update of user data is performed in accordance with a command, storing the user data in an appropriate free space within the flash memory device on a page-by-page basis, and, at this time, recording, in the address translation table, a correspondence between a logical page address based on an input address and an address of a page, in the flash memory device in which the user data is stored, and storing information for identifying the corresponding logical page address in the spare area of the page; a function of, when the storage apparatus is started, detecting at least a group of pages to which user data has been written since the most recent saving of the table; and a function of scanning the spare area of each of the group of pages and reproducing a state of the table as updated after the most recent saving of the table to reconstruct the table.

"According to another embodiment of the present invention, there is provided a computer system including: a storage apparatus that includes a flash memory device as a main memory, a second memory for storing an address translation table, and a control section configured to control the flash memory device and the second memory; and a host processing apparatus capable of accessing data in the flash memory device. The flash memory device is formed of a plurality of pages, each of the pages having a spare area. Data is stored on a page-by-page basis. The control section has: a function of saving the address translation table within the second memory to the flash memory device as appropriate; a function of, when writing or updating of user data is performed in accordance with a command from the processing apparatus, storing the user data in an appropriate free space within the flash memory device on a page-by-page basis, and, at this time, recording, in the address translation table, a correspondence between a logical page address based on an address inputted from the processing apparatus and an address of a page, in the flash memory device in which the user data is stored, and storing information for identifying the corresponding logical page address in the spare area of the page; a function of, when the storage apparatus is started, detecting at least a group of pages to which user data has been written since the most recent saving of the table; and a function of scanning the spare area of each of the group of pages and reproducing a state of the table as updated after the most recent saving of the table to reconstruct the table.

"According to yet another embodiment of the present invention, there is provided a method for managing a storage apparatus including a flash memory device as a main memory and a second memory for storing an address translation table. The method includes the steps of: allowing the flash memory device to be formed of a plurality of pages each having a spare area, data being stored on a page-by-page basis; when writing user data corresponding to a specific logical page address to the flash memory device, storing the user data in an appropriate free space within the flash memory device on a page-by-page basis; when storing the user data on a page-by-page basis, recording, in the address translation table, a correspondence between the logical page address and an address of a page, in the flash memory device in which the user data is stored; storing information for identifying the corresponding logical page address in the spare area of the page; saving the address translation table within the second memory to the flash memory device as appropriate; when a system is started, detecting at least a group of pages to which user data has been written since the most recent saving of the table; and scanning the spare area of each of the group of pages and reproducing a state of the table as updated after the most recent saving of the table to reconstruct the table.

"According to an embodiment of the present invention, when writing or updating of user data is performed in accordance with a command sent from a host, for example, under the control of the control section, the user data is stored in an appropriate free space within the flash memory on a page-by-page basis.

"At this time, the correspondence between the logical page address based on the address inputted from the host and the address of the page in the flash memory in which the user data is stored is recorded in the address translation table, and the information for identifying the corresponding logical page address is stored in the spare area of the page.

"Further, the address translation table within the second memory is saved to the flash memory device as appropriate.

"When the storage apparatus is started, at least a group of pages to which user data was written after the most recent saving of the table is detected, and the spare areas in the detected group of pages are scanned to reproduce the state of the table as updated after the most recent saving of the table, whereby complete reconstruction of the table is achieved.

"According to the an embodiment of the present invention, regardless of the capacity of the storage, the reconstruction of the address translation table is achieved for a very short time after the occurrence of an instantaneous power interruption. For example, the storage apparatus can be restarted in less than five seconds.

"Therefore, an user is seldom obliged to wait for a long time for the system to restart after the occurrence of the instantaneous power interruption. In addition, the storage apparatus can be used as a removable medium without a problem."

For more information, see this patent: Nishihara, Toshiyuki; Date, Kazuyuki. Storage Apparatus, Computer System, and Method for Managing Storage Apparatus. U.S. Patent Number 8745310, filed January 3, 2008, and published online on June 3, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8745310.PN.&OS=PN/8745310RS=PN/8745310

Keywords for this news article include: Sony Corporation.

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