News Column

"Low-Power States for a Computer System with Integrated Baseband" in Patent Application Approval Process

June 19, 2014



By a News Reporter-Staff News Editor at Computer Weekly News -- A patent application by the inventors Ahmad, Sagheer (Cupertino, CA); Cumming, Pete (Wickwar, GB); Simeral, Brad (San Francisco, CA); Longnecker, Matthew (San Jose, CA); Guha, Sudeshna (Bangalore, IN), filed on November 27, 2012, was made available online on June 5, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application is assigned to Nvidia Corporation.

The following quote was obtained by the news editors from the background information supplied by the inventors: "Computer systems continue to evolve, with ever faster processing speeds, greater data handling capabilities, and increasing storage capacity. Computers have also been steadily reduced in size. This size reduction is most apparent in the laptop, notebook, tablet, and hand-held computer markets (e.g., a smart phone). While desiring to continuously decrease the size and weight of laptops, notebooks, and hand-held computers, manufacturers have also steadily reduced the size and weight of on-board batteries. Because battery-life in laptops, notebooks, and hand-held computers is such an important consideration, power management methods are utilized to increase battery-life.

"Conventional computer systems may employ a multitude of power saving features for reducing system power, such as power conservation methods for graphical user interfaces, processors, and memory controllers, which for example, may include frequency reduction, clock-gating, power-gating, low-power DRAM states, low-power I/O modes, and disabling of analog circuits, such as phase-locked loops (PLLs) and delay-locked loops (DLLs). A coordinated engagement and disengagement of these low-power features can enable low-power system states to be utilized for power savings.

"However, any level of power-gating of a system component (e.g., a microprocessor, a memory controller) is time constrained based on power mode entry and exit delays. In other words, while deep power savings may be achieved through power-gating, such power-gating may not be permitted if the power-gating entry and exit times exceed prescribed timing constraints. For example, when placing a memory controller into a low-power state, the current state is saved to memory and the memory controller is then transitioned to the low-power state (e.g., the memory controller may be powered off). Later, when a wake-event is received, the memory controller is powered on and its state is restored. However, any resulting latency required to power on the memory controller and restore its previous state must be transparent to any agent requesting memory access. In other words, the deepest power-gating and power saving states may be unreachable because the resulting timing latency is too great."

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "Embodiments of this present invention provide solutions to the challenges inherent in managing low power states for computer systems with integrated basebands. In a method according to one embodiment of the present invention, a method for entering a power conservation state is disclosed. The method of entering a power conservation state comprises selecting and entering one of a plurality of low power states for the computer system in response to a detected system idle event. The one low power state is selected depending upon baseband module activity. The plurality of low power states comprise a first low power state and a second low power state for the computer system. A memory of the computer system is self-refreshed during the first low power state. A baseband module of the computer system remains powered, and the memory is accessible to the baseband module during the second low power state. The method also includes exiting from the one of a plurality of low power states when a wake event is detected.

"In a computer system according to one embodiment of the present invention, a computer system operable to select and enter a power conservation state is disclosed. The computer system comprises a baseband module, a memory controller, and a processor. The baseband module is operable to process paging events and to process voice calls. The processor and the baseband module are operable to access the memory via the memory controller. The computer system is further operable to enter one of a plurality of low power states in response to a detected system idle event. The one low power state is selected depending upon baseband module activity. The plurality of low power states comprise a first low power state and a second low power state. The memory of the computer system is self refreshed during the first low power state. The baseband module remains powered and the memory is accessible to the baseband module during the second low power state via the memory controller during the second low power state. The computer system is further operable to exit from the one of the plurality of low power states when a wake event is detected.

"In a computer system according to another embodiment of the present invention, the computer system comprises a baseband module, a processor, and a memory for storing instructions, that when executed by the computer system perform a method of entering a power conservation state. The method comprises selecting and entering one of a plurality of low power states for the computer system in response to a detected system idle event. The one low power state is selected depending upon baseband module activity. The plurality of low power states comprise a first low power state and a second low power state for the computer system. A memory of the computer system is self refreshed during the first low power state. A baseband module of the computer system remains powered, and the memory is accessible to the baseband module during the second low power state. The method also includes exiting from the one of a plurality of low power states when a wake event is detected.

BRIEF DESCRIPTION OF THE DRAWINGS

"Embodiments of the present invention will be better understood from the following detailed description, taken in conjunction with the accompanying drawing figures in which like reference characters designate like elements and in which:

"FIG. 1 illustrates an exemplary simplified block diagram of a system on chip with integrated baseband in accordance with an embodiment of the present invention;

"FIG. 2 illustrates an exemplary state diagram for managing low power states for a computer system with an integrated baseband in accordance with an embodiment of the present invention;

"FIG. 3 illustrates an exemplary computer implemented flow diagram for managing low power states for a computer system with an integrated baseband in accordance with an embodiment of the present invention; and

"FIG. 4 illustrates an exemplary simplified block diagram of a system on chip with integrated baseband incorporating secondary memory controller in accordance with an embodiment of the present invention."

URL and more information on this patent application, see: Ahmad, Sagheer; Cumming, Pete; Simeral, Brad; Longnecker, Matthew; Guha, Sudeshna. Low-Power States for a Computer System with Integrated Baseband. Filed November 27, 2012 and posted June 5, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=384&p=8&f=G&l=50&d=PG01&S1=20140529.PD.&OS=PD/20140529&RS=PD/20140529

Keywords for this news article include: Nvidia Corporation.

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Source: Computer Weekly News


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