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Researchers Submit Patent Application, "Snr Estimation in Analog Memory Cells", for Approval

May 13, 2014



By a News Reporter-Staff News Editor at Information Technology Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Ish-Shalom, Tomer (Raanana, IL); Dar, Ronen (Tel Aviv, IL), filed on October 22, 2012, was made available online on May 1, 2014.

The patent's assignee is Apple Inc.

News editors obtained the following quote from the background information supplied by the inventors: "Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell holds a certain level of a given physical quantity such as an electrical charge or voltage, which represents the data stored in the cell. The levels of this physical quantity are also referred to as analog storage values, storage values or analog values. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into regions, each region corresponding to a programming state or programming level that represents one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits.

"Some memory devices, which are commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible memory states. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible memory states.

"Flash memory devices are described, for example, by Bez et al., in 'Introduction to Flash Memory,' Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in 'Multilevel Flash Cells and their Trade-Offs,' Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.

"Eitan et al., describe another type of analog memory cell called Nitride Read Only Memory (NROM) in 'Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?' Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in 'A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate,' Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, Calif., Feb. 3-7, 2002, pages 100-101, which is incorporated herein by reference. Other exemplary types of analog memory cells are Floating Gate (FG) cells, Ferroelectric RAM (FRAM) cells, magnetic RAM (MRAM) cells, Charge Trap Flash (CTF) and phase change RAM (PRAM, also referred to as Phase Change Memory--PCM) cells. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in 'Future Memory Technology including Emerging New Memories,' Proceedings of the 24.sup.th International Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference.

"Analog memory cells are typically read by comparing their storage values to one or more read thresholds. Various methods for setting and adjusting read thresholds are known in the art. For example, U.S. Patent Application Publication 2010/0091535, whose disclosure is incorporated herein by reference, describes a method for operating a memory that includes a plurality of analog memory cells. The method includes storing data in the memory by writing first storage values to the cells. Second storage values are read from the cells, and a Cumulative Distribution Function (CDF) of the second storage values is estimated. The estimated CDF is processed so as to compute one or more thresholds. As another example, U.S. Pat. No. 8,000,135, whose disclosure is incorporated herein by reference, describes techniques for estimation of memory cell read thresholds by sampling inside programming level distribution intervals.

"U.S. Patent Application Publication 2011/0066902, whose disclosure is incorporated herein by reference, describes a system and method of reading data using a reliability measure. In some embodiments, a data storage device includes a memory array including a target memory cell and one or more other memory cells. The device also includes a controller coupled to the memory array. The controller is configured to directly compute a reliability measure for at least one bit stored in the target memory cell of the memory array based on a voltage value associated with the target memory cell and based on one or more corresponding voltage values associated with each of the one or more other memory cells of the memory array."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "An embodiment of the present invention that is described herein provides a method including programming a group of analog memory cells by writing respective analog values into the memory cells in the group. After programming the group, the analog values are read from the memory cells in the group using a set of read thresholds so as to produce readout results. Respective optimal positions for the read thresholds in the set are identified based on the readout results. A noise level in the readout results is estimated based on the identified optimal positions of the read thresholds.

"In some embodiments, estimating the noise level includes assessing the noise level responsively to a change between first and second estimations of the optimal positions at respective different times. In an embodiment, estimating the noise level includes assessing the noise level responsively to a distance between the optimal positions of first and second read thresholds in the set. Estimating the noise level may include assessing the noise level responsively to a distance between the optimal positions and respective current positions of the read thresholds using which the readout results were obtained.

"In some embodiments, the method includes computing reliability measures for the readout results based on the estimated noise level. Computing the reliability measures may include calculating a reliability measure for a readout result relating to a first read threshold in the set, based on the noise level estimated for a second read threshold in the set.

"There is additionally provided, in accordance with an embodiment of the present invention, a method including programming a group of analog memory cells by writing respective analog values into the memory cells in the group. After programming the group, the analog values are read from the memory cells in the group using a set of read thresholds so as to produce readout results. A measure of information entropy of the readout results is calculated, and a noise level in the readout results is estimated based on the calculated measure of the information entropy.

"In some embodiments, programming the group includes storing in the memory cells data represented by the analog values, and calculating the measure of the information entropy includes calculating mutual information for the readout results and for decoding results of the data. In another embodiment, calculating the measure of the information entropy includes evaluating an empirical entropy function over the readout results.

"There is also provided, in accordance with an embodiment of the present invention apparatus including an interface and storage circuitry. The interface is configured to communicate with a memory that includes analog memory cells. The storage circuitry is configured to program a group of the analog memory cells by writing respective analog values into the memory cells in the group, to read the analog values from the memory cells in the group, after programming the group, using a set of read thresholds so as to produce readout results, to identify, based on the readout results, respective optimal positions for the read thresholds in the set, and to estimate a noise level in the readout results based on the identified optimal positions of the read thresholds.

"There is further provided, in accordance with an embodiment of the present invention, apparatus including an interface and storage circuitry. The interface is configured to communicate with a memory that includes analog memory cells. The storage circuitry is configured to program a group of the analog memory cells by writing respective analog values into the memory cells in the group, to read the analog values from the memory cells in the group, after programming the group, using a set of read thresholds so as to produce readout results, to calculate a measure of information entropy of the readout results, and to estimate a noise level in the readout results based on the calculated measure of the information entropy.

"There is also provided, in accordance with an embodiment of the present invention, apparatus including a memory and storage circuitry. The memory includes analog memory cells. The storage circuitry is configured to program a group of the analog memory cells by writing respective analog values into the memory cells in the group, to read the analog values from the memory cells in the group, after programming the group, using a set of read thresholds so as to produce readout results, to identify, based on the readout results, respective optimal positions for the read thresholds in the set, and to estimate a noise level in the readout results based on the identified optimal positions of the read thresholds.

"There is further provided, in accordance with an embodiment of the present invention, apparatus including a memory and storage circuitry. The memory includes analog memory cells. The storage circuitry is configured to program a group of the analog memory cells by writing respective analog values into the memory cells in the group, to read the analog values from the memory cells in the group, after programming the group, using a set of read thresholds so as to produce readout results, to calculate a measure of information entropy of the readout results, and to estimate a noise level in the readout results based on the calculated measure of the information entropy.

"The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 is a block diagram that schematically illustrates a memory system, in accordance with an embodiment of the present invention;

"FIG. 2 is a graph showing programming level distributions in a group of analog memory cells, and associated read thresholds, in accordance with an embodiment of the present invention; and

"FIG. 3 is a flow chart that schematically illustrates a method for reading a group of analog memory cells, in accordance with an embodiment of the present invention."

For additional information on this patent application, see: Ish-Shalom, Tomer; Dar, Ronen. Snr Estimation in Analog Memory Cells. Filed October 22, 2012 and posted May 1, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=3666&p=74&f=G&l=50&d=PG01&S1=20140424.PD.&OS=PD/20140424&RS=PD/20140424

Keywords for this news article include: Apple Inc., Information Technology, Information and Data Storage.

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Source: Information Technology Newsweekly


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