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Researchers Submit Patent Application, "Semiconductor Devices and Methods of Fabricating the Same", for Approval

May 14, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventor PARK, Jemin (Suwon-si, KR), filed on October 11, 2013, was made available online on May 1, 2014.

No assignee for this patent application has been made.

News editors obtained the following quote from the background information supplied by the inventors: "Inventive concepts relate to semiconductor devices and methods of fabricating the same.

"Semiconductor devices are attractive in the electronic industry because of their small size, multi-function, and/or low fabrication costs. However, semiconductor devices have been highly integrated with the development of the electronic industry. Widths and spaces of patterns of the semiconductor devices have been more and more reduced for higher integration of the semiconductor devices. Recently, new and/or more expensive exposure techniques are required for fine patterns of the semiconductor devices, such that it is difficult to highly integrate the semiconductor device. Thus, various researches are being conducted for new integration techniques."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventor's summary information for this patent application: "Example embodiments of inventive concepts may provide semiconductor devices capable of suppressing (e.g., preventing and/or minimizing) leakage current.

"Example embodiments of inventive concepts also provide methods of fabricating ore highly integrated semiconductor devices capable of suppressing and/or resolving mask misalignment problems.

"In at least one example embodiment, a semiconductor device may include: a plurality of word lines in or on a substrate with a gate insulation layer therebetween, the plurality of word lines extending in a first direction; a plurality of bit lines on the substrate to cross over the word lines; and a bit line node contact connecting each of the plurality of bit lines to the substrate. Each bit line may have a width equal or substantially equal to a width of a corresponding bit line node contact.

"In at least one other example embodiment, a semiconductor device may include: at least two storage node contacts in or on a substrate; a bit line node contact in or on the substrate between the at least two storage node contacts; and a bit line on the bit line node contact between the at least two storage node contacts, the bit line node contact and the bit line being spaced apart from sidewalls of the at least two storage node contacts by a spacer.

"In at least one other example embodiment, a semiconductor device may include: at least two storage node contacts in or on a substrate; a bit line node contact on the substrate between the at least two storage node contacts; and a bit line on the bit line node contact between the at least two storage node contacts, each of the bit line node contact and the bit line being spaced apart from sidewalls of the at least two storage node contacts by substantially the same distance.

"In at least one other example embodiment, a semiconductor device may include: a plurality of word lines extending in a first direction in or on a substrate; a plurality of bit lines crossing over the plurality of word lines; and a plurality of bit line node contacts, each of the plurality of bit line node contacts connecting a corresponding bit line to the substrate, and each of the plurality of bit line node contacts having a width substantially equal to a width of the corresponding bit line.

"According to at least some example embodiments, a sidewall of a bit line may be aligned with a sidewall of a bit line node contact.

"The semiconductor device may further include: a storage node contact between the plurality of bit lines and connected to the substrate. The storage node contact may be insulated from the plurality of bit lines. A distance between a sidewall of a storage node contact and a bit line adjacent to the sidewall may be equal or substantially equal to a distance between another sidewall of the storage node contact and a bit line adjacent to the other sidewall.

"A distance between the bit line node contact and the storage node contact may be equal or substantially equal to a distance between the bit line and the storage node contact.

"According to at least some example embodiments, the semiconductor device may further include: a storage node pad between the storage node contact and the substrate. The storage node pad may have a width greater than a width of the storage node contact. A sidewall of the storage node pad may be aligned with a sidewall of the storage node contact.

"The semiconductor device may further include: a separation pattern between the adjacent storage node pads. The separation pattern may vertically overlap with a bit line.

"The semiconductor device may further include: a buried insulation layer between a bit line and the substrate at a side of a corresponding bit line node contact. A sidewall of the buried insulation layer may be aligned with a sidewall of the storage node contact.

"The semiconductor device may further include: an insulation spacer between a bit line and a corresponding storage node contact, and between a bit line node contact and the corresponding storage node contact. The insulation spacer may include an air gap.

"The semiconductor device may further include: a data storage element electrically connected to a storage node contact.

"At least one other example embodiment provides a method of fabricating a semiconductor device. According to at least this example embodiment, the method may include: forming a plurality of word lines extending in a first direction in or on a substrate; forming a first separation pattern crossing over the plurality of word lines; forming a buried insulation layer filling spaces between the first separation pattern; patterning the buried insulation layer to form a bit line node hole; recessing an upper portion of the buried insulation layer to expose upper sidewalls of the first separation pattern; forming a plurality of spacers covering the upper sidewalls of the first separation pattern and a sidewall of the bit line node hole; and forming a bit line and a bit line node contact, the bit line being between portions of the first separation pattern on the buried insulation layer, and the bit line node contact being in the bit line node hole.

"According to at least some example embodiments, the first separation pattern may be formed of a conductive material. In this case, the method may further include: removing a portion of the first separation pattern to form a storage node contact having a plug shape.

"The first separation pattern may be formed of an insulating material. In this case, the method may further include: removing a portion of the first separation pattern to form a storage node hole; and forming a storage node contact in the storage node hole.

"According to at least some example embodiments, the method may further include: removing the first separation pattern; and forming a storage node contact in a part of a region where the first separation pattern is removed.

"Before forming the first separation patterns, the method may further include: forming a capping pattern on each of the plurality of word lines, the capping pattern protruding from the substrate; forming a second separation pattern between adjacent portions of the capping pattern on the substrate; and forming a storage node pad between portions of the second separation pattern and between portions of the capping pattern, the storage node pad being connected to the substrate. In this case, forming the bit line node hole may include: removing a portion of the storage node pad and a portion of the second separation pattern.

"According to at least some example embodiments, forming the spacers may include: forming a sacrificial spacer covering the sidewall of the bit line node hole; forming an outer spacer covering a sidewall of the sacrificial spacer; and removing the sacrificial spacer to form an air gap. The sacrificial spacer may be formed of a hydrocarbon layer. In this case, removing the sacrificial spacer may include: performing an ashing process to decompose the sacrificial spacer.

BRIEF DESCRIPTION OF THE DRAWINGS

"Inventive concepts will become more apparent in view of the attached drawings and accompanying detailed description.

"FIG. 1A is a layout illustrating a semiconductor device according to example embodiments of inventive concepts;

"FIG. 1B is a perspective view illustrating a portion of FIG. 1A;

"FIG. 1C is a cross-sectional view taken along a line C-C' of FIG. 1A;

"FIGS. 2A and 2B are enlarge views of a portion 'P1' of FIG. 1C according to example embodiments of inventive concepts;

"FIGS. 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, and 11A are plan views illustrating an example embodiment of a method of fabricating a semiconductor device of FIG. 1A;

"FIGS. 3B, 4B, 5B, 6B, 7B, 7C, 8B, 9B, 9C, 10B, and 11B are perspective views illustrating an example embodiment of a method of fabricating a semiconductor device of FIG. 1B;

"FIG. 12A is a plan view illustrating a part of another example embodiment of a method of fabricating a semiconductor device of FIG. 1A;

"FIG. 12B is a perspective view illustrating a part of another example embodiment of a method of fabricating a semiconductor device of FIG. 1B;

"FIG. 13A is a plan view illustrating a semiconductor device according to still other example embodiments of inventive concepts;

"FIG. 13B is a cross-sectional view taken along lines D-D' and E-E' of FIG. 13A;

"FIGS. 14A, 15A, 16A, 17A, 18A, and 19A are plan views illustrating an example embodiment of a method of fabricating a semiconductor device of FIG. 13A;

"FIGS. 14B, 15B, 16B, 16C, 17B, 18B, and 19B are cross-sectional views illustrating an example embodiment of a method of fabricating a semiconductor device of FIG. 13B;

"FIG. 20 is a schematic block diagram illustrating an example of electronic devices including a semiconductor device according to example embodiments of inventive concepts; and

"FIG. 21 is a schematic block diagram illustrating an example of memory systems including semiconductor devices according to example embodiments of inventive concepts."

For additional information on this patent application, see: PARK, Jemin. Semiconductor Devices and Methods of Fabricating the Same. Filed October 11, 2013 and posted May 1, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=3693&p=74&f=G&l=50&d=PG01&S1=20140424.PD.&OS=PD/20140424&RS=PD/20140424

Keywords for this news article include: Patents, Electronics, Semiconductor.

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Source: Electronics Newsweekly


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