News Column

Researchers Submit Patent Application, "Power Management Control and Controlling Memory Refresh Operations", for Approval

May 14, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventor Klein, Dean A. (Eagle, ID), filed on December 24, 2013, was made available online on May 1, 2014.

The patent's assignee is Round Rock Research, Llc.

News editors obtained the following quote from the background information supplied by the inventors: "An essential data processing component is memory, such as a random access memory (RAM). RAM allows the user to execute both read and write operations on memory cells. Typically, semiconductor RAM devices are volatile, in that stored data is lost once the power source is disconnected or removed. Typical examples of RAM devices include dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM) and static random access memory (SRAM).

"In recent years, the memory capacity, i.e., the number and density of memory cells in memory devices have been increasing. Accordingly, the size of each cell (including storage capacitor size) has been shrinking, which also shortens the cell's data holding time. Typically, each row in a memory device receives a stabilizing refresh command in the conventional standardized cycle, about every 64 milliseconds. However, with increasing cell number and density, it is becoming more and more difficult to stabilize all memory cells at least once within the stabilizing cycle, e.g., it requires more power as well as a significant portion of the available bandwidth.

"DRAMS and SDRAMs are volatile in the sense that the stored data, typically in the form of charged and discharged capacitors contained in memory cells arranged in a large array, will dissipate the charge after a relatively short period of time because of a charge's natural tendency to distribute itself into a lower energy state. DRAM is particularly volatile in that each cell should be stabilized, i.e., refreshed, typically every 64 milliseconds, in order to retain information stored on its memory cells.

"Recently, studies have been conducted on the use of chalcogenide glasses as ionic conductors which can be used to build non-volatile memory cells. One such non-volatile memory device, which uses chalcogenide glass to form non-volatile memory cells is known as a programmable conductor RAM (PCRAM). See, for example, U.S. Patent publication number 2002/0123248.

"Although referred to as non-volatile memory elements, the PCRAM memory elements are more accurately nearly non-volatile memory ('NNV memory'). The NNV memory elements do require periodic refreshing, although the refreshing operations occur significantly more infrequently than refresh operations in standard volatile DRAM or SDRAM memory elements. Once a refreshing operation is complete, a memory device incorporating the NNV memory elements can be placed into an extremely low power state until either the system is returned to a normal operating state or until another refreshing operation is required.

"A memory system may comprise many memory devices. Although the amount of time allotted to a refresh operation is conventionally pre-determined and therefore static, each memory device may require a different amount of time to complete the refresh operation. The difference in the amount of time required for a refresh operation is caused by a variety of factors. For example, the difference may stem from inaccuracies and inefficiencies in the performance of a refresh operation, or it may be caused by differences in memory architectures of a memory device. Furthermore, the time a device requires for a refresh operation may vary due to various factors, such as amount of memory that needs refreshing. For example, if a refresh operation is performed as a burst operation, with all cells in all devices being refreshed in a series of sequential operations, even a small variation of individual cell refresh times accumulates into significant differences in the refresh times for the entire device containing the individual cells.

"The time allotted to perform a refresh operation is generally set at the maximum amount of time the devices could require to perform the refresh operation. Otherwise, if the time period is set too short, some devices may not complete the refresh operation before the time period expires. Thus, there is wasted time when the amount of time required for a refresh operation is shorter than the pre-determined, allotted refresh operation time.

"Similarly, the frequency of refreshing a memory system is conventionally static and predetermined. However, many factors affect the minimum frequency necessary to ensure retention of stored information. For example, in a memory system that includes NNV memory elements, ambient temperature affects the volatility of the NNV memory elements--the ambient temperature affects the ability of the memory elements to retain a stored state.

"It would be advantageous to have memory refresh techniques that reduce wasted time."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventor's summary information for this patent application: "Exemplary embodiments of the present invention provide memory refresh and power management circuitry whose operation can be affected by dynamic factors. The circuitry can also reduce time delays in refresh operations. The various embodiments of the invention may be used with any memory requiring refresh.

"Rather than allotting a pre-determined amount of time to complete the refresh operation, the memory refresh circuitry of an exemplary embodiment provides a refresh complete signal indicating when a burst self-refresh operation is complete. In a system with multiple memory devices, the refresh complete signals from the devices are combined. A power management circuit receives the refresh complete signal when the refresh operation has been completed.

"In another exemplary embodiment of the invention, a memory system monitors a condition, such as ambient or internal temperature, and initiates refresh operations based on the temperature. The system can include a circuit monitoring the ambient and internal temperatures, and the refresh circuitry can initiate a refresh operation in response. The refresh circuitry initiates a refresh operation based on either established set temperature points or the integration of temperature.

"Another exemplary embodiment of the invention is a combination of the embodiments described above. For example in this exemplary embodiment, a memory system provides memory refresh circuitry whose operation can be affected by dynamic factors and monitors a condition, such as ambient or internal temperature, and initiates refresh operations based on the temperature.

BRIEF DESCRIPTION OF THE DRAWINGS

"These and other features and advantages of the invention will be more readily understood from the following detailed description of the invention which is provided in connection with the accompanying drawings, in which:

"FIG. 1 depicts a block diagram of a memory system in accordance with an exemplary embodiment of the invention;

"FIG. 2 shows a block diagram of a memory device in FIG. 1 in greater detail in accordance with an exemplary embodiment of the invention;

"FIG. 3 shows a block diagram of the refresh counter of FIG. 2 in greater detail;

"FIG. 4 shows a block diagram of the power management controller of FIG. 1 in greater detail in accordance with an exemplary embodiment of the invention;

"FIG. 5 shows a block diagram of the power management controller of FIG. 1 in greater detail in accordance with another exemplary embodiment of the invention;

"FIG. 6 shows a memory system as in FIGS. 1-5 integrated on a semiconductor chip; and

"FIG. 7 shows a memory system as in FIGS. 1-5 integrated in a processing system."

For additional information on this patent application, see: Klein, Dean A. Power Management Control and Controlling Memory Refresh Operations. Filed December 24, 2013 and posted May 1, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=3656&p=74&f=G&l=50&d=PG01&S1=20140424.PD.&OS=PD/20140424&RS=PD/20140424

Keywords for this news article include: Electronics, Semiconductor, Random Access Memory, Round Rock Research Llc.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


For more stories covering the world of technology, please see HispanicBusiness' Tech Channel



Source: Electronics Newsweekly


Story Tools






HispanicBusiness.com Facebook Linkedin Twitter RSS Feed Email Alerts & Newsletters