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Researchers Submit Patent Application, "Coherence Controller Slot Architecture Allowing Zero Latency Write Commit", for Approval

May 13, 2014

By a News Reporter-Staff News Editor at Information Technology Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Pierson, Matthew D. (Murphy, TX); Chirca, Kai (Dallas, TX); Anderson, Timothy D. (University Park, TX), filed on October 18, 2013, was made available online on May 1, 2014.

The patent's assignee is Texas Instruments Incorporated.

News editors obtained the following quote from the background information supplied by the inventors: "This invention concerns multi-core data processing systems. It is typical in such multi-core systems for each core to have its own local cache memory and for all the cores to share a common higher level memory. This could be a memory on the same integrated circuit as the multiple cores (on chip) or an external memory (off chip). In such a multi-core data processing system more than one core may write to the same higher level memory. A multi-core shared memory controller must coordinate memory traffic between the multiple cores and the shared memory.

"This task includes contrary goals of maintaining coherence and suitable memory access latency. Each time one of the multiple cores updates a cache entry corresponding to an address in shared memory, the multi-core shared memory controller must insure that other cores operate upon the latest version of the data. Conflicts may occur if the data is cached by more than one core. The prior art typically handles this by a snoop cycle. The multi-core shared memory controlled polls (snoops) the caches of other cores to determine whether they store the address of interest. The response may be no, the cache doesn't store the data. Upon a yes response, meaning the cache stores the data, the remote cache determines if its cache data is dirty. A dirty cache entry is one that has been updated locally since the last update to the shared memory. If the remote cache entry is clean, then it signals the multi-core shared memory controller. This situation presents no conflict with the operation triggering the snoop. If the remote cache entry is dirty, the multi-core shared memory controller must reconcile the data stored in the two (or more) caches. It is possible that the separate caches have updated the same cache line but not the same data. In this case the dirty portion of the cache lines should be merged before writing to the shared memory. If the separate caches updated the same date, they need to be written to the shared memory in proper order to maintain coherence.

"These coherence operations take memory cycles and buffer space that is disadvantageous to the system in operational speed and/or integrated circuit area."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "This invention speeds operation for coherence writes to the shared memory. One prior art technique stalls writing the coherence data pending snoop responses. This typically prevents the endpoint memory from servicing any other accesses during the wait for snoop responses. An alternate prior art technique commits the write immediately and stores the coherence write data pending snoop responses for reconciliation. This prior art technique requires storing a lot of data for the snoop reconciliation. This invention immediately commits to the memory endpoint the coherence write data. Thus this data will be available earlier than if the memory controller stalled this write pending snoop responses. This invention computes write enable strobes for the coherence write data based upon the cache dirty tags. Determination of write enable strobes for this data write was a typical feature of the prior art. This invention stores only the write byte enable strobes rather than both these strobes and the coherence data for snoop data reconciliation. These stored write enable strobes enable determination of which data to write to the endpoint memory upon a cached and dirty snoop response.


"These and other aspects of this invention are illustrated in the drawings, in which:

"FIG. 1 illustrates the organization of a typical digital signal processor to which this invention is applicable (prior art);

"FIG. 2 illustrates details of a very long instruction word digital signal processor core suitable for use in FIG. 1 (prior art);

"FIG. 3 illustrates the pipeline stages of the very long instruction word digital signal processor core illustrated in FIG. 2 (prior art);

"FIG. 4 illustrates the instruction syntax of the very long instruction word digital signal processor core illustrated in FIG. 2 (prior art);

"FIG. 5 illustrates the details of a set of typical prior art cache lines (prior art);

"FIG. 6 illustrates a computing system including a local memory arbiter according to an embodiment of the invention;

"FIG. 7 illustrates a preferred embodiment of the multi-core shared memory controller of this invention;

"FIG. 8 illustrates a detail of one embodiment of a portion of the multi-core shared memory controller of constructed to practice this invention; and

"FIGS. 9A, 9B and 9C together illustrate operation of this invention."

For additional information on this patent application, see: Pierson, Matthew D.; Chirca, Kai; Anderson, Timothy D. Coherence Controller Slot Architecture Allowing Zero Latency Write Commit. Filed October 18, 2013 and posted May 1, 2014. Patent URL:

Keywords for this news article include: Information Technology, Texas Instruments Incorporated, Information and Data Processing.

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Source: Information Technology Newsweekly

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