News Column

Patent Issued for Storage System, Control Method Therefor, and Program

May 13, 2014



By a News Reporter-Staff News Editor at Information Technology Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Koseki, Hideyuki (Machida, JP); Nonaka, Yusuke (Sagamihara, JP), filed on May 27, 2009, was published online on April 29, 2014.

The assignee for this patent, patent number 8713251, is Hitachi, Ltd. (Tokyo, JP).

Reporters obtained the following quote from the background information supplied by the inventors: "Disk array devices, when configured to constitute RAID (Redundant Array of Independent (or Inexpensive) Disks), enable parallel operation of multiple disks and thus realize data reading and data writing requested by a host at high speed. In such disk array devices, redundant data corresponding to an RAID level such as Mirror or Parity is created in order to provide high fault tolerance to protect against disk failure.

"Further, in the disk array devices, a verification code for detecting data corruption and errors in a destination address that could occur during transfer is appended to received data for the purpose of improving the reliability of the whole system. For example, in data writing, data received from a host is divided into logical data blocks each having a constant data length, and a verification code is appended to each logical data block, so that the logical data having the verification code appended thereto is stored in a cache memory or a disk. After that, when data reading is requested by the host, a verification code of the relevant data is checked before the data is transferred to the host, whereby it is ensured that the data to be transferred to the host is identical to the data that has been written.

"As a specific example of such verification codes, a technique of appending an LRC (Longitudinal Redundancy Check) code for detecting data bit errors that could occur during transfer and also appending an LA (Logical Address) for detecting address errors is typically known (see Patent Literature 1). In recent years, a DIF (Data Integrity Field) proposed by T10, which is a storage interfaces technical committee, has been spreading as a standard format of a verification code.

"There are also cases in which an interface device that supports the process of creating/appending and checking/deleting such a verification code is used as a host adapter of a disk array device. In such cases, in data writing, a disk adapter, which is an entrance of a disk array device, appends a verification code to data received from a host. Meanwhile, in data reading, the disk adapter checks for the integrity of the verification code. Accordingly, it is possible to ensure that a data error or data loss has not occurred in the device."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "Technical Problem

"A disk array device such as the one illustrated in Patent Literature 1 checks for the presence or absence of data errors (such as data corruption or data loss) with the use of a verification code in data reading. However, in such a technique, whether or not data has been accurately written to a cache memory in data writing is not ensured. Typical disk array devices have a high-speed, low-capacity cache memory in order to improve the I/O (Input/Output) processing performance, and an asynchronous writing process is performed in data writing. In this process, upon storage of data transferred from a host into a cache memory, the host is notified of the completion of data transfer, and thereafter, the data in the cache memory is written to a disk device at a given timing.

"Therefore, in the disk array device such as the one disclosed in Patent Literature 1, there is a possibility that the session of the data transfer from the host could be closed without the data accurately written to a cache memory due to a transfer error that occurs during data writing. That is, the host could erroneously determine that data transfer has ended normally upon reception of the information about the completion of data transfer from the disk array device, and thus could close the transfer session. After that, even if the disk array device detects errors in the data in the cache memory, it would be impossible to issue a data retransmission request to the host. Accordingly, data loss could occur in which the disk array device loses the received data.

"Accordingly, in order to ensure that data has been accurately stored in a cache memory, it is necessary to check a verification code of data stored in the cache memory so as to check for the presence or absence of transfer errors before notifying the host of the completion of data transfer.

"The present invention has been made in view of the foregoing, and it is an object of the present invention to provide a technique of preventing the occurrence of data loss by ensuring that data has been accurately written to a cache memory.

"Solution to Problem

"In the present invention, a method of checking the address portion of a verification code is used as a means of ensuring the successful data transfer to a cache memory. It should be noted that, however, that when only the address portion is checked, it would be impossible to detect if data in the cache has been accurately updated/overwritten. This is because, the address portion will not change either before or after the overwrite, and thus the check result of the address portion will be always the same whenever it is checked.

"Thus, according to the present invention, a check bit for verifying the successful update/overwrite is also provided in a verification code, and both the address information and the check bit are checked so as to verify the successful overwrite.

"First, in overwriting, a check bit of a verification code appended to data to be overwritten, which is in a cache memory, is set to '1' indicative of non-updated data, before the initiation of data transfer from a host. Then, a data transfer request is issued to the host and a host adapter is instructed to assign '0,' indicative of updated data, to a check bit of a verification code appended to data transferred from the host. Since a verification code with a check bit of '0' indicative of updated data is appended to the data transferred from the host adapter to the cache memory, if the data in the cache memory is accurately updated, the check bit that has been preset to '1' should be updated to '0'. Therefore, after the completion of data transfer to the cache memory, it is possible to determine if there is any address error and if the data has been surely updated by checking only the address portion and the check bit of the verification code appended to the updated data.

"That is, a disk array device of the present invention includes a memory (160), a transfer processor (110), and a memory controller (150). In the memory (160), old data (301) to be updated is stored that has a verification code (310) including a positional information (342, 351) of the data in a disk unit (200) and a check information (341) for ensuring the successful writing. The memory controller (150), upon receiving a write request of new data (302) for updating the old data (301) from an external device (40), changes the check information (341) of the old data (301) to an information different from a check information (341) to be appended to the new data (302), and then instructs the external device (40) to initiate transfer of the new data (302). The transfer processor (110) appends a verification code (310), which includes a positional information (342, 351) and a check information (341) for ensuring the successful writing, to the new data (302) received from the external device (40), and transfers the new data with the verification code appended thereto to the memory (160). Accordingly, when the new data (302) has been accurately written to the memory (160), the check information (341) that has been changed is changed back to the original check information (341). Note that the memory controller (150) references information that specifies the old data (301) included in the write request, and checks if the old data (301) to be updated is present in the memory (160). If it is determined to be present in the memory (160), the memory controller (150) changes the check information (341) of the old data (301).

"In addition, the transfer processor (110) sends information about the completion of the writing of the new data (302) to the memory (160) from the memory controller (150) to the external device (40).

"The transfer processor (110) may be configured to create multiple data blocks (300) by dividing the new data (302) into multiple groups each having a predetermined length (for example, 512 bytes) and append the verification code (310) to each data block (300). In that case, the memory controller (150) is configured to write the new data (302) to the memory (160) per data block (300) and change the check information (341) that has been changed back to the original check information (341).

"In addition, the memory controller (150) checks if the new data (302) is the right data by comparing the positional information (342, 351) of the verification code (310) appended to the new data (302) with the setting information (16240) indicating a position of the disk unit (200) to which the new data (302) should be written.

"Further, when the verification code (310) includes a data error detection code (320) for detecting data errors, the memory controller (150) may be configured to compare information obtained by computing the new data (302) written to the memory (160) with the data error detection code (320), and if the two match, determine that the new data (302) has been successfully written to the memory (160).

"Further features of the present invention will become apparent from the following description of embodiments and the accompanying drawings.

"Advantageous Effects of Invention

"According to the present invention, the possibility of data loss that could occur in a disk array device can be reduced, whereby the reliability of data in the disk array device can be improved.

"Further, it is also possible to detect update/overwrite errors of data in a cache memory, which cannot be detected when only the address portion of the verification code is checked."

For more information, see this patent: Koseki, Hideyuki; Nonaka, Yusuke. Storage System, Control Method Therefor, and Program. U.S. Patent Number 8713251, filed May 27, 2009, and published online on April 29, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=20&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=986&f=G&l=50&co1=AND&d=PTXT&s1=20140429.PD.&OS=ISD/20140429&RS=ISD/20140429

Keywords for this news article include: Hitachi Ltd., Information Technology, Information and Data Loss and Recovery.

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Source: Information Technology Newsweekly


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