News Column

Patent Issued for Methods for Fabricating Semiconductor Devices

May 14, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Park, Sang-Jine (Yongin-si, KR); Kwon, Kee-Sang (Seoul, KE); Yun, Doo-Sung (Suwon-si, KR); Yoon, Bo-Un (Seoul, KR); Yoon, Il-Young (Hwaseong-si, KR); Han, Jeong-Nam (Seoul, KR), filed on June 5, 2012, was published online on April 29, 2014.

The patent's assignee for patent number 8709942 is Samsung Electronics Co., Ltd. (KR).

News editors obtained the following quote from the background information supplied by the inventors: "Embodiments of the present inventive concepts relate to methods for fabricating semiconductor devices.

"In the fabrication of semiconductor-based transistor devices, it is commonplace for photo masks to be employed for the various required etching steps. However, with increased integration of semiconductor devices, the number of required etching steps is increasing, as is the depth of an etched feature relative to its width. Accordingly, the resulting processing variation can increase by a proportional amount. In order to minimize processing variation, a hard mask process has recently been proposed to perform etching steps. More recently, in order to increase etching selectivity, a metal hard mask has also been introduced."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "Embodiments of the present inventive concepts provide a method for fabricating a semiconductor device, which can form a damascene-type wire in a manner that offers improved reliability and improved processing efficiency. This can result in a device that offers reduced process variation and improved reliability.

"In an aspect, a method for fabricating a semiconductor device comprises: providing a substrate including an interlayer dielectric layer and first and second hard mask patterns sequentially stacked thereon; providing a first trench in the interlayer dielectric layer through the second hard mask pattern and the first hard mask pattern; providing a filler material on the interlayer dielectric layer and the second hard mask pattern to fill the first trench; exposing an upper portion of the second hard mask pattern by partially removing the filler material; removing the second hard mask pattern; removing remaining filler material from the first trench; and forming a wiring by filling the first trench with a conductive material.

"In some embodiments, the second hard mask pattern comprises a metal mask pattern.

"In some embodiments, the second hard mask pattern comprises titanium nitride (TiN).

"In some embodiments, the removing of the second hard mask pattern comprises selectively removing the second hard mask pattern using wet etching.

"In some embodiments, the partially removing the filler material is performed using at least one of a chemical mechanical polishing (CMP) process, an etch-back process, or a combination thereof.

"In some embodiments, the providing the substrate comprises providing a substrate including an etch stopper layer formed between the substrate and the interlayer dielectric layer, and a lower dielectric layer formed between the substrate and the etch stopper layer, the lower dielectric layer having a conductive contact formed therein.

"In some embodiments, the removing the remaining filler material comprises exposing the etch stopper layer by removing the filler material, and, prior to filling the first trench with the conductive material, there is further provided exposing the conductive contact by removing the etch stopper layer exposed by the first trench.

"In some embodiments, the method further comprises, prior to the providing the filler material to fill the first trench, exposing the conductive contact by removing the etch stopper layer exposed by the first trench.

"In another aspect, a method for fabricating a semiconductor device comprises: providing a substrate including an interlayer dielectric layer thereon, the substrate including a first region and a second region; sequentially forming a first hard mask pattern and a second hard mask pattern on the interlayer dielectric layer in the first and second regions; providing a first trench in the interlayer dielectric layer in the first region and providing a second trench in the interlayer dielectric layer in the second region using the first hard mask pattern and the second hard mask pattern as etch masks; filling the first trench and the second trench by providing a filler material on the interlayer dielectric layer and the second hard mask pattern in the first and second regions; exposing an upper portion of the second hard mask pattern by partially removing the filler material; removing the second hard mask pattern; removing remaining filler material from the first trench and the second trench; and forming a wiring by filling the first french and the second trench with a conductive material.

"In some embodiments, after the providing of the first trench and the second trench, the first hard mask pattern in the first region has a first thickness, and the second hard mask pattern in the second region has a second thickness, wherein the first thickness is different than the second thickness.

"In some embodiments, the second hard mask pattern comprises a metal mask pattern.

"In some embodiments, the removing the second hard mask pattern comprises selectively removing the second hard mask pattern using wet etching.

"In some embodiments, the providing the substrate comprises providing a substrate including an etch stopper layer between the substrate and the interlayer dielectric layer, and a lower dielectric layer between the substrate and the etch stopper layer and having a conductive contact formed therein.

"In some embodiments, the removing the remaining filler material comprises exposing the etch stopper layer by removing the filler material, and prior to filling the first trench with the conductive material, there is further provided exposing the conductive contact by removing the etch stopper layer exposed by the first trench.

"On some embodiments, the method further comprises, prior to the filling the first trench, exposing the conductive contact by removing the etch stopper layer exposed by the first trench.

"In another aspect, a method of fabricating a semiconductor device, comprises: providing a first hard mask layer on an interlayer dielectric film and providing a second hard mask layer on the first hard mask layer, the second hard mask layer having etch selectivity relative to the first hard mask layer; forming a trench through the second hard mask layer, the first hard mask layer and the interlayer dielectric film, the trench forming a first opening through the first hard mask layer and the trench forming a second opening through the second hard mask layer, the first opening being larger in area that the second opening; filling the trench with a filler material, the filler material filling the trench in the interlayer dielectric film, and the first and second openings; removing the second hard mask layer; removing filler material from the first trench; and filling the first trench with a conductive material to form an inter-layer wiring.

"In some embodiments, filling the first trench further comprises the filler material covering upper portions of the second hard mask layer.

"In some embodiments, the method further comprises partially removing the filler material to expose upper portions of the second hard mask layer prior to removing filler material from the first trench.

"In some embodiments, the interlayer dielectric film is provided on a substrate and further comprising an etch stopper layer between the substrate and the interlayer dielectric film, wherein the etch stopper layer is selectively removed at a bottom of the first trench prior to filling the first trench with the filler material.

"In some embodiments, the interlayer dielectric film is provided on a substrate and further comprising an etch stopper layer between the substrate and the interlayer dielectric film, wherein the etch stopper layer is selectively removed at a bottom of the first trench after removing the filler material from the first trench."

For additional information on this patent, see: Park, Sang-Jine; Kwon, Kee-Sang; Yun, Doo-Sung; Yoon, Bo-Un; Yoon, Il-Young; Han, Jeong-Nam. Methods for Fabricating Semiconductor Devices. U.S. Patent Number 8709942, filed June 5, 2012, and published online on April 29, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=86&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=4273&f=G&l=50&co1=AND&d=PTXT&s1=20140429.PD.&OS=ISD/20140429&RS=ISD/20140429

Keywords for this news article include: Semiconductor, Samsung Electronics Co. Ltd..

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Source: Electronics Newsweekly


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