The patent's inventors are Lee, Meng-Jung (Taoyuan County, TW); Wang, Ting-Hsiung (
This patent was filed on
From the background information supplied by the inventors, news correspondents obtained the following quote: "The present invention relates to a method of generating an integrated circuit model, and more particularly, a method of generating the integrated circuit model by tracing current paths originated from nodes on a circuit connection net-list.
"In conventional tests or simulations on an integrated circuit, confirming power domains for interface pins in the integrated circuit, isolation information of the power domain, and accurate operating voltages of the power domain are commonly performed tasks.
"However, in these tests or simulations on the integrated circuit, information about the power domain or the operating voltages are required to be set manually, i.e., engineers for designing these tests or simulations are required to judge and input the information about the power domain or the operating voltage by himself or herself. Some defects may occur because: (1) There may be leakages occurring on paths between an interface pin and its corresponding power node or its corresponding ground node; (2) It takes too long to test or to simulate each interface pin; (3) Certain interface pins may be missed while establishing an interface pin list.
"During tests or simulations on an integrated circuit, the abovementioned isolation information is also required to be set manually. Manual setting the isolation information may cause defects such as: (1) It takes too long to test or to simulate each interface pin; (2) Certain information of isolated elements may be missed in an established integrated circuit voltage model so that errors occur in results of the tests or simulations. Besides, while performing isolation tests or simulations on the integrated circuit according to the manually-set isolation information, it is time-consuming to prepare to simulate the integrated circuit. Worse yet, at least two times of simulations may be required for ensuring certain elements which should be turned off can be turned off at precise timings. Therefore, time consumption cannot be neutralized while performing isolation tests or simulations on the integrated circuit according to the manually-set isolation information."
Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "The claimed invention discloses a method of generating an integrated circuit model, which may be recorded in medium to be executed by a microprocessor. The method comprises generating a circuit isolation node file according to a circuit connection net-list and an isolation cell topology; generating an interface node voltage net-list according to the circuit connection net-list and a pin voltage information spec file; and generating an integrated circuit voltage model according to the circuit isolation node file and the interface node voltage net-list.
"These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings."
For the URL and additional information on this patent, see: Lee, Meng-Jung; Wang, Ting-Hsiung; Lo, Yu-Lan; Kao, Shu-Yi. Method of Generating Integrated Circuit Model. U.S. Patent Number 8713497, filed
Keywords for this news article include: Electronics,
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