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Patent Issued for Method of Forming Micropattern, Method of Forming Damascene Metallization, and Semiconductor Device and Semiconductor Memory Device...

May 14, 2014



Patent Issued for Method of Forming Micropattern, Method of Forming Damascene Metallization, and Semiconductor Device and Semiconductor Memory Device Fabricated Using the Same

By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Park, In-sun (Seoul, KR); Choi, Gil-heyun (Seoul, KR); Park, Ji-soon (Suwon-si, KR); Lee, Jong-myeong (Seongnam-si, KR); Hong, Jong-won (Hwaseong-si, KR); Kim, Hei-seung (Suwon-si, KR), filed on June 26, 2012, was published online on April 29, 2014.

The assignee for this patent, patent number 8709937, is Samsung Electronics Co., Ltd. (Suwon-Si, KR).

Reporters obtained the following quote from the background information supplied by the inventors: "Example embodiments of inventive concepts relate to a method of forming a micropattern, a method of forming a damascene metallization, and a semiconductor device fabricated using the same, and more particularly, to a method of forming a micropattern, a method of a damascene metallization, and a semiconductor device and a semiconductor memory device fabricated using the same.

"To meet demands for the integration of semiconductor devices, pitches of metal lines are being decreased. Shapes of the lines of the dummy region may affect formation of active lines due to an optical proximity effect with the fineness of lines."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "Example embodiments of inventive concepts relate to a method of forming a micropattern.

"Example embodiments of inventive concepts relate to a method of forming a damascene metallization by which dummy lines can be formed without sacrificing any one of a photolithography side and a conductor burying side of fabricating.

"Example embodiments of inventive concepts relate to a semiconductor device having dummy lines fabricated using the methods.

"Example embodiments of inventive concepts relate to a semiconductor memory device having dummy lines fabricated using the methods.

"According to example embodiments of inventive concepts, a method of forming micropatterns on a substrate having a dummy region adjacent to an active line region, includes forming a first mask covering at least a part of the dummy region and exposing a portion of the substrate, forming mold mask patterns on the first mask and the exposed substrate, forming spacers on sidewalls of the mold mask patterns, forming second masks by removing parts of the first mask exposed through the mold mask patterns and the spacers, removing the mold mask patterns, and forming the micropatterns by etching the substrate using the spacers and the second masks as etch masks. The first mask may cover all of the dummy region. Patterns having widths wider than widths of patterns of the active line region may be obtained in the dummy region through the etching of the substrate. The substrate may include two active line regions which are adjacent to each other so that the dummy region is between the active line regions, and the mold mask patterns may include crossing sub-patterns which connect the two active line regions.

"At least some of the mold mask patterns may have line-and-space sub-patterns across the active line region and the dummy region. Lines of the line-and-space sub-patterns may be arranged at uniform intervals. A ratio between widths of the lines of the line-and-space sub-patterns and widths of spaces of the line-and-space sub-patterns may be between about 1:2.5 and about 1:3.

"At least one of the lines of the at least some of the mold mask patterns of the dummy region may extend to at least an end of the first mask.

"The forming the spacers may include forming a spacer material layer on the substrate, the first mask, and the mold mask patterns, and anisotropically etching the spacer material layer, wherein an end of at least one of lines of the at least some of the mold mask patterns of the dummy region exists on the first mask, a distance between the end of the line of the at least some of the mold mask patterns and an end of the first mask positioned in a direction in which the line of the at least some of the mold mask patterns extends may be greater than a thickness of the spacer material layer. A distance between the end of the line of the at least some of the mold mask patterns and a most adjacent mold mask patterns except for the line of the at least some of the mold mask patterns may be greater than two times the thickness of the spacer material layer.

"The forming the spacers may include forming a spacer material layer on the substrate, the first mask, and the mold mask patterns, and anisotropically etching the spacer material layer, wherein two adjacent lines of the lines of the at least some of the mold mask patterns of the dummy region have narrower widths at ends of the two adjacent lines than at other parts of the two adjacent lines, and a bridge spacer is on sidewalls of the mold mask patterns except for the two adjacent lines and the bridge spacer connects to spacers on the two adjacent lines. The substrate may include two active line regions that are adjacent to each other so that the dummy region is between the two active regions, and the bridge spacer may on sidewalls of the parts of the mold mask patterns connecting the two active line regions.

"According to example embodiments of inventive concepts, a method of forming micropatterns includes forming mold mask patterns on an active line region and a dummy region of a substrate, the mold mask patterns including sidewalls and line-and-space sub-patterns having the equal widths and distances, forming spacers on sidewalls of the mold mask patterns, forming a first mask that covers the mold mask patterns and the spacers of the dummy region and exposes a part of the mold mask patterns, removing the part of the mold mask patterns exposed after forming the first mask to leave a remaining mold mask pattern, removing the first mask, and etching the substrate using the spacers and the remaining mold mask patterns as etch masks. The active line region may be adjacent to the dummy region.

"A ratio between a width of the lines of the line-and-space sub-patterns and a width of the spaces of the line-and-space sub-patterns may be between about 1:2.5 and about 1:3. An end of at least one of the lines of the mold mask patterns of the dummy region may have an end positioned underneath the first mask to overlap with the first mask. Ends of at least two adjacent lines of the lines of the mold mask patterns of the dummy region may be positioned underneath the first mask to overlap with the first mask.

"The first mask may cover all of the dummy region. The substrate may include two active line regions which are adjacent to each other so that the dummy region between the active line region, and the mold mask patterns may include crossing sub-patterns that connect the two adjacent active line regions.

"The forming spacers may include forming a spacer material layer on the substrate and the mold mask patterns, anisotropically etching the spacer material layer. An end of at least one of lines of the mold mask patterns of the dummy region may be under the first mask, and a distance between the end of the at least one line of the dummy region and an end of the first and the crossing sub-patterns may be smaller than two times the thickness of the spacer material layer.

"The forming spacers may include forming a spacer material layer on the substrate and the mold mask patterns, and anisotropically etching the spacer material layer, wherein an end of at least one of lines of the mold mask patterns of the dummy region is under the first mask, and a distance between the end of the line and an end of the first mask positioned in a direction in which the line extends is greater than the thickness of the spacer material layer.

"A distance between the line and a most adjacent line of the mold mask patterns may be greater than two times the thickness of the spacer material layer. Patterns having widths wider than widths of patterns of the active line region may be obtained in the dummy region through the etching of the substrate.

"The substrate may include a first insulating layer, an etch stop layer formed on the first insulating layer, a second insulating layer formed on the etch stop layer. The etching of the substrate using the spacers and the remaining mold mask patterns as the etch masks may include recessing the second insulating layer using the spacers and the remaining mold mask patterns as etch masks. The method may further include burying a conductive material in the recesses after etching the substrate. The conductive material may be Cu or a Cu alloy.

"According to example embodiments of inventive concepts, a method of forming damascene metallization on a substrate includes forming a first mask on a substrate. The substrate may include a dummy region adjacent to an active line region, a first insulating layer, an etch stop layer on the first insulating layer, a second insulating layer on the etch stop layer, and a sacrificial layer on the second insulating layer. The first mask may cover at least a part of the dummy region and expose a portion of the substrate. The method further includes forming mold mask patterns on the first mask and the exposed portion of the substrate, forming spacers on sidewalls of the mold mask patterns; removing a part of the first mask exposed through the mold mask patterns and the spacers to form second masks; removing the mold mask patterns; etching the sacrificial layer and a second insulating layer using the spacers and the second masks as etch masks to form recesses; and forming a conductive material in the recesses. The conductive material may be a copper (Cu) or a Cu alloy.

"According to example embodiments of inventive concepts, a method of forming damascene metallization includes forming dummy patterns having first widths on a dummy region of a substrate, and forming cell patterns having second widths on an active line region of the substrate. The active line region may be adjacent to the dummy region and the second widths may be less than the first widths. The method further includes forming a seed layer on the active line region and the dummy region, forming a conductive material layer on a whole surface of the substrate, and planarizing the conductive material layer to form metal lines.

"The forming the conductive material layer may be performed using electroplating. The planarization of the conductive material layer may be performed using chemical mechanical polishing (CMP) or etch back. The cell patterns and the dummy patterns may be simultaneously formed.

"The forming the dummy patterns may include forming mold mask patterns in the dummy region, and forming a first mask on or underneath the mold mask patterns of the dummy region.

"According to example embodiments of inventive concepts, a semiconductor device includes a semiconductor substrate that includes an active line region and a dummy region adjacent to the active line region; a plurality of cell lines which are disposed in cell trenches formed in the active line region; and a plurality of dummy lines which are disposed in dummy trenches formed in the dummy region, wherein distances among the dummy lines are wider than distances among the cell lines.

"The dummy lines may include two or more dummy lines, wherein ends of the two or more dummy lines are connected to one another. The dummy lines may include one or more dummy lines, wherein widths of ends of the dummy lines are wider than widths of another parts of the dummy lines.

"According to example embodiments of inventive concepts, a semiconductor memory device includes a string selection line (SSL) and a ground selection line (GSL) on a substrate, a group of wordlines extending in a first direction between the string selection line (SSL) and the ground selection line (GSL), a first bitline set and a second bit line set on the group of wordlines, the first bitline set and the second bitline set extending in a second direction that is different from the first direction, the first bitline set and the second bitline set being electrically connected to the SSL, a common source line (CSL) which is electrically connected to the GSL, and a plurality of dummy bitlines between the first and second bitline sets. The dummy bitlines may be separated by a first distance that is greater than a second distance separating at least two bitlines of the first bitline set.

"The semiconductor memory device may further include CSL taps electrically connected to the CSL. A level of the CSL taps may be equal to levels of the dummy bitlines.

"A level of the CSL may be higher than levels of the wordlines and lower than levels of the first and second bitline sets. The dummy bitlines may be physically connected to the SSL through vias. At least two or more dummy bitlines are connected to one another.

"According to example embodiments of inventive concepts, a method of forming micropatterns includes forming mold mask patterns on a substrate, the mold mask patterns including at least two first mold structures on an active line region of the substrate and at least two second mold structures on a dummy region of the substrate, the at least two first and second mold structures each having sidewalls; forming a spacer pattern including first spacers on the sidewalls of the at least two first mold structures, and second spacers on the sidewalls of the at least two second mold structures, forming the micropattern by removing a portion of the active line region of the substrate not covered by the first spacers, and removing a portion of the dummy region of the substrate not covered by the at least two second mold structures and the second spacers.

"The method may include forming a first mask that covers all of the dummy region of the substrate. The forming mold mask patterns on the substrate may include forming the at least two second mold structures on the first mask. The forming a spacer pattern may include forming the second spacers on the first mask. The forming the micropatterns forming a second mask by etching a part of the first mask exposed between the second spacers, removing the at least two first and second mold structures, and etching the substrate using the first and second spacers and the second mask an etch mask.

"The method may include forming a first mask that covers all of the dummy region of the substrate, the at least two second mold structures, and the second spacers; removing the at least two first mold structures after forming the first mask; and removing the first mask after removing the at least two first mold structures. The forming the micropatterns may include etching the substrate using the first spacers, the at least two second mold structures, and the second spacers as an etch mask.

"According to example embodiments of inventive concepts, a method of forming damascene metallization may include the foregoing method of forming micropatterns, wherein the substrate further includes a first insulating layer, an etch sop layer on the first insulating layer, and a sacrificial layer on the second insulating layer. The forming the micropatterns may include forming first recesses by removing a portion of the sacrificial layer and the second insulating layer in the active line region of the substrate that is not covered by the first spacers, and forming second recesses by removing a portion of the sacrificial layer and the second insulating layer in the dummy region of the substrate that is not covered by the at least two second mold structures and the second spacers. The method further includes forming a conductive material in the first and second recesses."

For more information, see this patent: Park, In-sun; Choi, Gil-heyun; Park, Ji-soon; Lee, Jong-myeong; Hong, Jong-won; Kim, Hei-seung. Method of Forming Micropattern, Method of Forming Damascene Metallization, and Semiconductor Device and Semiconductor Memory Device Fabricated Using the Same. U.S. Patent Number 8709937, filed June 26, 2012, and published online on April 29, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=86&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=4278&f=G&l=50&co1=AND&d=PTXT&s1=20140429.PD.&OS=ISD/20140429&RS=ISD/20140429

Keywords for this news article include: Semiconductor, Samsung Electronics Co. Ltd..

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Source: Electronics Newsweekly