News Column

Patent Issued for Method for Testing Multi-Chip Stacked Packages

May 13, 2014



By a News Reporter-Staff News Editor at Journal of Technology -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventor Chang, Kai-Jun (Hsinchu, TW), filed on September 23, 2011, was published online on April 29, 2014.

The patent's assignee for patent number 8710859 is Powertech Technology Inc. (Hsinchu, TW).

News editors obtained the following quote from the background information supplied by the inventors: "Multi-chip packaging is an advanced high-density packaging technology to vertically stacking a plurality of dice within the same package. The existing packaging method is to stack individual chips onto a substrate followed by corresponding packaging and testing processes. However, using a substrate increases overall package thickness and footprint.

"In order to reduce the dimension of a multi-chip package, there is an attempt to stack a plurality of chips using wafer-to-wafer bonding to manufacture a substrate-less chip cube such as related technology revealed in US Patent No. 2011/0074017. However, bad chips are always randomly present within a wafer, therefore, wafer-to-wafer bonding would cause overall packaging yield of substrate-less chip cubes to drop. Moreover, when a substrate is eliminated, the pitch between the external electrical electrodes or/and the testing electrodes of a chip cube is shrunk from a few hundred micrometer down below a hundred micrometer so that the existing pogo pins of a tester for conventional semiconductor packages can not be used. There are two solutions to resolve the shrunk pitch issue. The first one is to directly SMT bond the substrate-less chip cube onto a board without any testing followed by a module test without ensuring the electrical joints between the stacked chips good or bad. The other one is to directly mount the substrate-less chip cube onto an interposer (normally made of Si) with fan-out circuitry and fan-out electrodes then load the interposer into a tester having pogo pins to perform testing where the overall testing cost is quite complicated and expensive."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventor's summary information for this patent: "The main purpose of the present invention is to provide a method for testing multi-chip stacked packages to achieve fine-pitch probing of substrate-less chip cubes which can easily be integrated into TSV packaging processes.

"The second purpose of the present invention is to provide a method for testing multi-chip stacked packages to test one or more substrate-less chip cubes before SMT on boards and to reduce the number of adhering steps of adhesive tapes to achieve lower packaging cost and to prevent SMT bonding bad substrate-less chip cube on boards.

"According to the present invention, a method for testing multi-chip stacked packages is revealed. Firstly, one or more substrate-less chip cubes are provided, each of which consisting of a plurality of vertically stacked chips where a stacked gap is formed between two adjacent chips and each substrate-less chip cube has a plurality of testing electrodes disposed on a top chip surface. Then, the substrate-less chip cubes are attached onto an adhesive tape where the testing electrodes are away from the adhesive tape with the adhesive tape attached inside an opening of a tape carrier. Then, a filling encapsulant is disposed on the adhesive tape to fully fill the stacked gaps between adjacent chips. Then, the tape carrier is fixed on a wafer testing carrier so that the substrate-less chip cubes can be loaded into a wafer tester without releasing from the adhesive tape. Finally, a plurality of testing probes of a probe card mounted on the probe head of a wafer tester probe on the testing electrodes to electrically test the substrate-less chip cubes."

For additional information on this patent, see: Chang, Kai-Jun. Method for Testing Multi-Chip Stacked Packages. U.S. Patent Number 8710859, filed September 23, 2011, and published online on April 29, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=68&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=3360&f=G&l=50&co1=AND&d=PTXT&s1=20140429.PD.&OS=ISD/20140429&RS=ISD/20140429

Keywords for this news article include: Powertech Technology Inc..

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Source: Journal of Technology


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