News Column

Patent Issued for Memory Interface Circuit, Memory Interface Method, and Electronic Device

May 14, 2014

By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventor Kato, Yoshiharu (Kasugai, JP), filed on November 18, 2011, was published online on April 29, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8711643 is assigned to Fujitsu Semiconductor Limited (Yokohama, JP).

The following quote was obtained by the news editors from the background information supplied by the inventors: "A DDR-SDRAM is a memory that outputs data at both rising and falling edges of a clock. The DDR-SDRAM outputs a read data signal and a data strobe signal, which is synchronized with the read data signal. The memory interface circuit, which is a request origin of data transfer, refers to the rising edge and the falling edge of the data strobe signal to accurately retrieve the read data signal.

"When starting the reading of data, a data strobe line for transmitting the data strobe signal is in a high impedance state during a period in which data is not output from the DDR-SDRAM. After a data read command is input, the data strobe line is set to a low level one cycle prior to when data is output from the memory. Such a low level period is referred to as a preamble period.

"A delay circuit is used to divide the data strobe signal into a plurality of data strobe signals having different delay widths. This obtains a plurality of data strobe signals having different input timings. An L period detection circuit distinguishes the phase of the data strobe signals, which are delayed differently by the delay circuit. Further, when the data strobe signal has a low level for a period of one cycle, the L period detection circuit detects the low level period as the preamble period. Japanese Laid-Open Patent Publication No. 2008-293279 describes such a technique for detecting the preamble period of the data strobe signal.

"If an internal circuit retrieves the read data signal when the data strobe signal has high impedance, the internal circuit may function erroneously."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventor's summary information for this patent: "According to one aspect, a memory interface circuit includes a gating circuit that starts detection of a logic level of a data strobe signal in accordance with a data read command. A clamp circuit clamps the data strobe signal to a first logic level after the data read command is issued. A detection circuit detects a logic level of the data strobe signal, which is driven by a memory, in accordance with the data read command.

"Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.

"It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed."

URL and more information on this patent, see: Kato, Yoshiharu. Memory Interface Circuit, Memory Interface Method, and Electronic Device. U.S. Patent Number 8711643, filed November 18, 2011, and published online on April 29, 2014. Patent URL:

Keywords for this news article include: Electronics, Fujitsu Semiconductor Limited.

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Source: Electronics Newsweekly