News Column

Patent Issued for Early Kill Removal Graphics Processing System and Method

May 14, 2014



By a News Reporter-Staff News Editor at Journal of Engineering -- Nvidia Corporation (Santa Clara, CA) has been issued patent number 8711155, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Hutchins, Edward A. (Mountain View, CA); Angell, Brian K. (San Jose, CA).

This patent was filed on May 14, 2004 and was published online on April 29, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems facilitate increased productivity and cost reduction in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Electronic systems designed to produce these results usually involve interfacing with a user and the interfacing often involves presentation of graphical images to the user. Displaying graphics images traditionally involves intensive data processing and coordination requiring considerable resources and often consuming significant power.

"An image is typically represented as a raster (an array) of logical picture elements (pixels). Pixel data corresponding to certain surface attributes of an image (e.g. color, depth, texture, etc.) are assigned to each pixel and the pixel data determines the nature of the projection on a display screen area associated with the logical pixel. Conventional three dimensional graphics processors typically involve extensive and numerous sequential stages or 'pipeline' type processes that manipulate the pixel data in accordance with various vertex parameter values and instructions to map a three dimensional scene in the world coordinate system to a two dimensional projection (e.g., on a display screen) of an image. A relatively significant amount of processing and memory resources are usually required to implement the numerous stages of a traditional pipeline.

"A number of new categories of devices (e.g., such as portable game consoles, portable wireless communication devices, portable computer systems, etc.) are emerging where size and power consumption are a significant concern. Many of these devices are small enough to be held in the hands of a user making them very convenient and the display capabilities of the devices are becoming increasingly important as the underlying fundamental potential of other activities (e.g., communications, game applications, internet applications, etc.) are increasing. However, the resources (e.g., processing capability, storage resources, etc.) of a number of the devices and systems are usually relatively limited. These limitations can make retrieving, coordinating and manipulating information associated with a final image rendered or presented on a display very difficult or even impossible. In addition, traditional graphics information processing can consume significant power and be a significant drain on limited power supplies, such as a battery."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "A present invention pixel processing system and method provides efficient processing of pixel information by treating pixels differently that do not contribute to image display. Embodiments of a present invention pixel processing system and method also permit complicated three dimensional images to be rendered with shallow graphics pipelines including reduced gate counts. The present invention also facilitates power conservation by pixel packet payloads associated with pixels that do not contribute to an image display presentation (e.g., pixels that are occluded).

"In one embodiment pixel packet information is received at a pipestage of a graphics pipeline. For example, receiving pixel packet information includes retrieving pixel surface attribute values in a single unified data fetch stage. A determination is made if the pixel packet information contributes to an image display presentation. For example, an analysis is performed to if a pixel associated with the pixel packet information is occluded (e.g., a depth comparison of Z values may be performed). The pixel packet information processing is handled in accordance with results of this determination. Pixel surface attribute values incorporated in the pixel packet information are forwarded for further downstream processing if the pixel surface attribute values contribute to the image display presentation. The pixel surface attribute values and pixel packet information may be removed from further processing if the pixel surface attribute values do not contribute to the image display presentation. In one exemplary implementation, the pixel packet includes a plurality of rows and the handling is coordinated for the plurality of rows. In one embodiment, multiple pipestages may remove occluded pixel information.

"In one embodiment, flow of a plurality of pixel packets into the unified single data fetch graphics pipeline stage is controlled by an upstream pipestage. The controlling includes maintaining sufficient slackness by regulating the input pixel flow to prevent stalling in the pipeline operating on the plurality of pixel packets. The controlling also includes permitting information associated with another one of the plurality of pixel packets to flow into the unified single data fetch graphics pipeline stage if the pixel packet information associated with the first pixel packet is removed from further processing. In one exemplary implementation, the flow control is provided by a gatekeeper stage which is notified if the pixel packet information is removed from further processing. Pipestages that remove occluded pixels therefore notify the gatekeeper when an occluded pixel is removed.

"In one embodiment, a plurality of pipestages downstream from the gatekeeper can eliminate pixel packets that belong to occluded pixels, upon each pixel so characterized, the respective pipestage notifies the gatekeeper so that more pixels may be allowed into the pipeline. In one embodiment, an upstream data fetch pipestage makes the occlusion determination, as described above. In another embodiment, any of the plurality of downstream pipestages can also make the occlusion determination. In effect, the removal of pixel packets from the pipeline, due to occlusion increases slack in the pipeline. In response to the slack increase, the gatekeeper allows more pixels into the pipeline."

For the URL and additional information on this patent, see: Hutchins, Edward A.; Angell, Brian K.. Early Kill Removal Graphics Processing System and Method. U.S. Patent Number 8711155, filed May 14, 2004, and published online on April 29, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=62&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=3066&f=G&l=50&co1=AND&d=PTXT&s1=20140429.PD.&OS=ISD/20140429&RS=ISD/20140429

Keywords for this news article include: Nvidia Corporation.

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Source: Journal of Engineering


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