News Column

Patent Issued for Aware Manufacturing of Integrated Circuits

May 14, 2014

By a News Reporter-Staff News Editor at Journal of Engineering -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Scheffer, Louis K. (Campbell, CA); Fujimura, Akira (Saratoga, CA), filed on March 24, 2010, was published online on April 29, 2014.

The assignee for this patent, patent number 8713484, is Cadence Design Systems, Inc. (San Jose, CA).

Reporters obtained the following quote from the background information supplied by the inventors: "An integrated circuit ('IC') is a device (e.g., a semiconductor device) that includes many electronic components, such as transistors, resistors, diodes, etc. These components are often interconnected to form multiple circuit components, such as gates, cells, memory units, arithmetic units, controllers, decoders, etc. An IC includes multiple layers of wiring that interconnect its electronic and circuit components.

"Design engineers design IC's by transforming logical or circuit descriptions of the IC's components into geometric descriptions, called layouts. IC layouts typically include (1) circuit modules (i.e., geometric representations of electronic or circuit IC components) with pins, and (2) interconnect lines (i.e., geometric representations of wiring) that connect the pins of the circuit modules. A net is typically defined as a collection of pins that need to be connected. To create layouts, design engineers typically use electronic design automation ('EDA') applications. These applications provide sets of computer-based tools for creating, editing, and analyzing IC design layouts.

"Fabrication foundries ('fabs') manufacture ICs based on these IC design layouts. To fabricate an IC after designing of the IC layout is completed, a lithographic plate (photomask) is created based on the IC layout so that the photomask contains the various geometries of the IC layout. The various geometries contained on the photomask represent the IC elements (such as IC components, interconnect lines, via pads, etc.) to be created on a wafer in a particular circuit pattern, the wafer forming the base of the integrated circuit.

"In some circumstances, some fabs are not able to manufacture ICs based on an IC design layout that is otherwise valid. This is due to the fact that the IC design layout requires certain manufacturing capabilities/settings that the fab does not have. As such, these IC design layouts do not take into account manufacturing constraints. Accordingly, because of these manufacturing constraints, the IC design layout needs to be modified to account for these manufacturing constraints. However, such modifications are made after the IC design layout is designed and sent over to the fabs.

"Thus, there is a need in art for a set of computer-based tools that are capable of factoring constraints of the manufacturing process (e.g. lithography process). Similarly, there is a need in art for a set of manufacturing processes that are aware of constraints used to design an IC."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "Some embodiments of the invention provide a manufacturing aware process for designing an integrated circuit ('IC') layout. The process receives a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture an IC based on the IC layout. The process defines a set of design rules based on the specified manufacturing configuration. The process uses the set of design rules to design the IC layout.

"Some embodiments of the invention provide a design aware process for manufacturing an integrated circuit ('IC'). The process receives an IC design with an associated set of design properties. The process specifies a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture the IC, where the specified set of manufacturing settings are based on the set of design properties. The process manufactures the IC based on the manufacturing settings.

"In some embodiments, the set of design properties includes a set of characteristics of the design. In some embodiments, the set of design characteristics includes (1) a particular dimensional attribute for a set of elements for a particular layer of the IC layout, and/or (2) a particular amount of wiring in a particular direction on a particular layer, etc.

"In some embodiments, the set of design properties includes a set of design rules. In some embodiments of the invention, the set of design rules specify a set of dimensional attributes of geometric elements of the IC layout. In some embodiments, these geometric elements can include modules, routes, vias, contacts, etc. The set of dimensional attributes of a geometric element can include the size, width, shape, rotation, orientation, spacing, density, distance and/or pitch in some embodiments.

"In some embodiments, the set of manufacturing settings include the stepper lens configuration and type, the aperture setting, the exposure setting and/or the light wavelength setting for each layer of the IC."

For more information, see this patent: Scheffer, Louis K.; Fujimura, Akira. Aware Manufacturing of Integrated Circuits. U.S. Patent Number 8713484, filed March 24, 2010, and published online on April 29, 2014. Patent URL:

Keywords for this news article include: Cadence Design Systems Inc.

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Source: Journal of Engineering

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