News Column

Patent Issued for Architecture for Accelerated Computer Processing

May 13, 2014



By a News Reporter-Staff News Editor at Information Technology Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventor Fiorini, Pierre (Issy-les-Molineaux, FR), filed on March 13, 2009, was published online on April 29, 2014.

The assignee for this patent, patent number 8713545, is Silkan (Meudon, FR).

Reporters obtained the following quote from the background information supplied by the inventors: "The invention relates to the field of computers which have to process intensive loads. This may involve computer systems dedicated to graphical applications or numerical calculation applications, but it may also involve processors included in signal or data processing chains. Intensive computing machines may be of different types. In most cases, they comprise a plurality of processors among which the parts of an application will be distributed, while the processors share common memory areas. In SMP (Shared Memory MultiProcessor) architectures, the processing operations are distributed among at least two processors which share access to the same common memory. In Distributed Memory Multiprocessor architectures, the distribution of the processing operations will depend on the relative locations of the different processors and stored data, i.e. on the physical architecture and not only on the application. A different form of parallelism may result from processor command instruction sets. This occurs, for example, in the case of SIMD (Single Instruction, Multiple Data) processing operations, in support of which specific instruction sets have been added to the normal instructions. Different instruction sets are thus known, notably SSE (Streaming SIMD Extensions) or AltiVec (trademark registered by Apple, IBM and Freescale Semiconducteurs to designate an SIMD instruction set operating on 128-bit vectors). Acceleration techniques also exist which are based on the realization that a single processor may be perfectly adapted to some of the processing operations that a computer has to perform, whereas, for certain applications, it may require assistance in the form of an additional processor installed on an add-on accelerator card. In this case, the traditional architecture most often involves all of the specialized applications being executed on the add-on card processor. The host structure processor is then underutilized since it will only manage the input/output from the additional processor. For given performance levels, this may result in the need to overdimension the add-on card processor, which will inevitably incur additional cost. The architecture is therefore not optimal."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventor's summary information for this patent: "The present invention solves this optimality problem by providing means for distributing the processing operations of applications having intensive computing requirements among the host processor(s) and the add-on card processor(s).

"For this purpose, the present invention discloses a data processing system including a host computer, an additional computer, an application module comprising a first executable code, a module for analyzing said first executable code and a module for generating a second executable code segmented notably into code blocks which are executed in a preferential manner on one of the two computers, wherein said second executable code comprises a sub-module for managing the distribution of the processing operations between the host computer and the additional computer and a sub-module for managing the additional computer as a virtual machine which executes the blocks allocated to said additional computer.

"Advantageously, the analysis module of said data processing system receives as input the first executable code of said application and supplies notably as output metadata comprising the input points of code blocks likely to constitute computing hotspots, the data structures used by said hotspots and the libraries of subroutines called by said first executable code.

"Advantageously, the metadata at the output of the analysis module constitutes input of the module for generating the second executable code.

"Advantageously, the metadata at the output of the analysis module are validated or modified when the second executable code is executed.

"Advantageously, the second executable code is executed in a preferential manner in user mode on the host computer.

"Advantageously, the second executable code uses specifically optimized functions installed on a driver which connects the additional computer to the host computer.

"Advantageously, the sub-module for managing the distribution of the processing operations between the host computer and the additional computer is programmed to control the execution of the basic blocks on the host computer.

"Advantageously, the sub-module for managing the distribution of the processing operations between the host computer and the additional computer is programmed to allow the second executable code to control the application for the execution on the additional computer of blocks chosen on the basis of parameterizable criteria and to regain control of the application at the end of the execution of each block.

"Advantageously, the sub-module for managing the distribution of the processing operations between the host computer and the additional computer is programmed so that the blocks of the second executable code are copies of blocks of the first executable code, said blocks of the first executable code being saved in a cache memory.

"Advantageously, the sub-module for managing the distribution of the processing operations between the host computer and the additional computer includes instructions to detect the most active code blocks.

"Advantageously, the sub-module for managing the distribution of the processing operations between the host computer and the additional computer is programmed in such a way as to switch the execution of the application to the blocks of the first executable code in order to process exceptions.

"Advantageously, the sub-module for managing the distribution of the processing operations between the host computer and the additional computer is programmed to make copies of the application context according to parameterizable rules.

"Advantageously, the sub-module for managing the distribution of the processing operations between the host computer and the additional computer includes a sub-module for managing a cache memory for executing the application in which the selected data structures are stored to be called by the blocks executed on the additional computer.

"Advantageously, the sub-module for managing the additional computer is programmed to execute libraries of subroutines corresponding to execution profiles and semantics defined for specific applications. Advantageously, a virtual machine corresponding to a specific application is dynamically loadable before the launch of said application by the environment.

"Advantageously, one of the profiles defines the additional computer as a vector machine.

"Advantageously, one of the profiles defines the additional computer as suitable for operating according to a flow computing model.

"Advantageously, the sub-module for managing the additional computer includes a high-level programming interface for programming the libraries for each profile.

"Advantageously, the sub-module for managing the additional computer includes a low-level programming interface for programming the second executable code.

"The use of an architecture according to the invention also offers the advantage that it allows the cost/performance ratio to be improved by an order of magnitude. Moreover, the system offers great versatility and can be optimized for different applications and hardware environments."

For more information, see this patent: Fiorini, Pierre. Architecture for Accelerated Computer Processing. U.S. Patent Number 8713545, filed March 13, 2009, and published online on April 29, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=14&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=696&f=G&l=50&co1=AND&d=PTXT&s1=20140429.PD.&OS=ISD/20140429&RS=ISD/20140429

Keywords for this news article include: Silkan, Information Technology, Information and Data Processing, Information and Data Architecture.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


For more stories covering the world of technology, please see HispanicBusiness' Tech Channel



Source: Information Technology Newsweekly


Story Tools






HispanicBusiness.com Facebook Linkedin Twitter RSS Feed Email Alerts & Newsletters