News Column

Patent Issued for 3D Solid-State Arrangement for Solid State Memory

May 13, 2014



By a News Reporter-Staff News Editor at Journal of Technology -- A patent by the inventor Franca-Neto, Luiz M. (Sunnyvale, CA), filed on January 26, 2012, was published online on April 29, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8711597 is assigned to HGST Netherlands B.V. (Amsterdam, NL).

The following quote was obtained by the news editors from the background information supplied by the inventors: "Embodiments of the present invention generally relate to a phase change memory (PCM) cell and an arrangement thereof.

"PCM is a type of non-volatile memory technology. PCM is an emerging technology and a candidate for storage class memory (SCM) applications and a serious contender to dislodge NOR and NAND flash memory in solid state storage applications and, in the case of NAND flash, solid-state drives (SSDs). PCM functions based upon switching a memory cell, typically based on chalcogenides such as Ge.sub.2Sb.sub.2Te.sub.5, between two stable states, a crystalline state and an amorphous state, by heating the memory cell. To heat the memory cell, an electrical current flows through the PCM cell. For an effective memory device, numerous PCM cells will be present in an array. Each of the PCM cells needs to be addressed, programmed and read with low overhead electrical wiring. The PCM cell is the phase-change cell itself, and PCM device, as discussed herein, is the set of PCM cells plus accompanying heaters (represented by a resistor in the electrical diagrams). The PCM device is the memory element herein.

"An array 100 of PCM cells is frequently arranged with a selecting transistor 102 in series with each memory cell 104 as shown in FIG. 1A. Word lines (WL) and bitlines (BL) are arranged so that each memory cell 104 can be programmed or queried. A row of PCM cells is activated by a single word line WL and each one of the PCM cells 104 in that row will affect the bitline BL to which it is electrically connected according to the state of the PCM cells 104, i.e. according to the PCM cells 104 being in their high (amorphous) or low (crystalline) resistance state. As shown in FIG. 1A, a simple array 100 of PCM devices 106 is shown. The array 100 is a two dimensional array because the PCM devices 106 are all arranged along a common plane.

"In an alternative design commonly named 'cross-point', shown in FIG. 1B. Each interception of word lines WL in the x direction and bit lines BL in the y direction has a PCM device 106, which includes the PCM cell 104 itself and its heater (represented by a resistor). Frequently, a selecting device is added in series with the PCM device. This selecting device can be a diode or a transistor. The selecting device, diode or transistor, added to the cross-point array 110, or alternatively, used externally to the array of PCM cells may frequently become the limiting factor on how dense can the PCM array become.

"When the selecting device is added to the cross-point array, there will be one selecting device per PCM device 106. Current requirements of the PCM device 106 need to be met by the selecting device. In consequence, even when the PCM device 106 can be made small to the lithographic limit and occupy only 4F.sup.2 of area, where F is the half-pitch critical dimension in a lithographic technology, the selecting device might require 30F.sup.2 if it is a CMOS transistor or 10F.sup.2 if it is a bipolar transistor. Optimized diodes, where efforts to make them very conductive might attend the current requirement of a PCM device using 4F.sup.2 area and are therefore very frequently considered as selecting device in cross point memories using PCM or any memory device requiring significant currents for operation.

"Unfortunately, using diodes makes it very difficult to extend the concept of cross-point array 110 from a two-dimensional (2D) array to a three-dimensional (3D) array. In a 3D array, addressing the PCM devices 106 that are in the middle of the array is difficult.

"Therefore, there is a need for a PCM device that permits each PCM cell to be accessed individually while minimizing the use of the surface area of the substrate over which the PCM device is disposed as well as minimizing the overhead wiring utilized to address PCM cells in the middle of the PCM 3D array."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventor's summary information for this patent: "The present invention generally relates to PCM cells and arrangements thereof. Even though the descriptions use PCM devices, this is only used for illustrative purposes. Other memory devices, such as a tunnel magnetoresistance (TMR) memory device, can be used as well without departing from the spirit of this invention. In one embodiment, a three-dimensional memory array comprises a first macro cell and a second macro cell. The first macro cell comprises a first three-terminal selecting device, which could be a metal semiconductor field effect transistor (MESFET) or another three-terminal selecting device; a first electrical connector coupled to the first three-terminal selecting device, the first electrical connector extending along a first axis and a second axis perpendicular to the first axis; a second electrical connector coupled to the first three-terminal selecting device; a first memory cell coupled to the second electrical connector, the first memory cell disposed along the second axis; and a third electrical connector coupled to the first memory cell, the third electrical connector extending along the second axis and a third axis perpendicular to both the second axis and the first axis. The a second macro cell comprises a second three-terminal selecting device; a fourth electrical connector coupled to the second three-terminal selecting device, the fourth electrical connector extends along a fourth axis that is parallel to the first axis, the fourth electrical connector also extends along the second axis, the fourth electrical connector is electrically coupled to the first electrical connector; a fifth electrical connector coupled to the second three-terminal selecting device; a second memory cell coupled to the fifth electrical connector, the second memory cell disposed along the second axis; and a sixth electrical connector coupled to the second memory cell, the sixth electrical connector extending along the second axis and a fifth axis that is parallel to the third axis, the sixth electrical connector is electrically coupled to the third electrical connector. An electrically insulating spacer is coupled between the third electrical connector and the fourth electrical connector.

"In another embodiment, a three-dimensional memory array comprises a first macro cell and a second macro cell. The first macro cell comprises a first three-terminal selecting device; a first electrical connector coupled to the first three-terminal selecting device, the first electrical connector extending along a first axis and a second axis perpendicular to the first axis; a second electrical connector coupled to the first three-terminal selecting device; a first memory cell coupled to the second electrical connector, the first memory cell disposed along the second axis; and a third electrical connector coupled to the first memory cell, the third electrical connector extending along the second axis and a third axis perpendicular to both the second axis and the first axis. The second macro cell comprises a second three-terminal selecting device; a fourth electrical connector coupled to the second three-terminal selecting device, the fourth electrical connector extends along the first axis and a fourth axis that is parallel to the second axis and the second electrical connector is electrically coupled to the first electrical connector; a fifth electrical connector coupled to the second three-terminal selecting device; a second memory cell coupled to the fifth electrical connector, the second memory cell disposed along the fourth axis; and a sixth electrical connector coupled to the second memory cell, the sixth electrical connector extending along the fourth axis and a fifth axis that is parallel to the third axis.

"In another embodiment, a three-dimensional memory array comprises a first macro cell, a second macro cell, and a third macro cell. The first macro cell comprises a first three-terminal selecting device; a first electrical connector coupled to the first three-terminal selecting device, the first electrical connector extending along a first axis and a second axis perpendicular to the first axis; a second electrical connector coupled to the first three-terminal selecting device; a first memory cell coupled to second electrical connector, the first memory cell disposed along the second axis; and a third electrical connector coupled to the first memory cell, the third electrical connector extending along the second axis and a third axis perpendicular to both the second direction and the first direction. The second macro cell comprises a second three-terminal selecting device; a fourth electrical connector coupled to the second three-terminal selecting device, the fourth electrical connector extends along the second axis and a fourth axis parallel to the first axis, the fourth electrical connector is electrically coupled to the first electrical connector; a fifth electrical connector coupled to the second three-terminal selecting device; a second memory cell coupled to the fifth electrical connector, the second memory cell disposed along the second axis; and a sixth electrical connector coupled to the second memory cell, the sixth electrical connector extending along the second axis and a fifth axis parallel to the third axis, the sixth electrical connector is electrically coupled to the third electrical connector. The three-dimensional memory array also comprises a first electrically insulating spacer coupled between the third electrical connector and the fourth electrical connector. The third macro cell comprises a third three-terminal selecting device; a seventh electrical connector coupled to the third three-terminal selecting device, the seventh electrical connector extending along the first axis and a sixth axis parallel to the second axis, the seventh electrical connector is electrically coupled to the first electrical connector; an eighth electrical connector coupled to the third three-terminal selecting device; a third memory cell coupled to the eighth electrical connector, the third memory cell disposed along the sixth axis; and a ninth electrical connector coupled to the third memory cell, the ninth electrical connector extending along the sixth axis and a seventh axis parallel to the third axis."

URL and more information on this patent, see: Franca-Neto, Luiz M.. 3D Solid-State Arrangement for Solid State Memory. U.S. Patent Number 8711597, filed January 26, 2012, and published online on April 29, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=53&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=2630&f=G&l=50&co1=AND&d=PTXT&s1=20140429.PD.&OS=ISD/20140429&RS=ISD/20140429

Keywords for this news article include: Technology, HGST Netherlands B.V..

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Source: Journal of Technology