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Researchers Submit Patent Application, "Secure Circuit Integrated with Memory Layer", for Approval

June 5, 2014



By a News Reporter-Staff News Editor at Politics & Government Week -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventor MINASSIAN, George (Santa Clara, CA), filed on November 9, 2012, was made available online on May 22, 2014.

The patent's assignee is Crossbar, Inc.

News editors obtained the following quote from the background information supplied by the inventors: "Security is a major concern for many applications of integrated circuits. Organizations invest considerable resources into the configuration of circuits, and many of these organizations wish to protect that investment. Circuits in certain applications may present inherent security concerns, such as circuits used for missile guidance systems or other sensitive military and government applications.

"Due to the value of the information contained in integrated circuits, considerable efforts have been made in reverse engineering by both government and industry. Circuit transmissions can be monitored and decrypted, and the circuits themselves can be physically deconstructed by successive etching operations. Imaging operations such as scanning electron microscopy (SEM) can be conducted between successive etches to discover circuit architecture. Other imaging techniques can be used when a circuit is in operation to directly or indirectly detect heat or electricity.

"Conventional methods for securing communication between integrated circuits and memory have been directed to encrypting the communications. However, this method has disadvantages. Communication circuitry is difficult to obscure, and therefore can be tapped by a dedicated reverse engineer. As technology develops, decryption techniques become more advanced, so communications that are secure today become less secure over the lifetime of a device. Some devices, such as certain aerospace applications, can have a long service life, so it is possible for current encryption techniques to become vulnerable during the lifetime of a device. In addition, if the key becomes known, access to a data stream is an undesirable vulnerability."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventor's summary information for this patent application: "Embodiments of the present invention may overcome one or more problems associated with circuit security, for example by embedding a security key on one or more memory layer disposed over a logic layer in a circuit device.

"In one embodiment, a secure circuit device includes a logic layer, one or more memory layers comprising non-volatile memory cells disposed over the circuit layer and integrated with the logic layer, a plurality of connectors provided between the logic layer and the one or more memory layers to electrically couple the logic layer and the one or more memory layers, and a security key disposed in the non-volatile memory cells of at least one memory layer, the security key being a key required for enabling access to the logic layer for operation.

"The security circuit may include a first memory layer and a second memory layer, and non-volatile memory cells storing the security key may be one time programmable memory cells. The non-volatile memory cells may be resistive memory cells arranged in a crossbar configuration.

"In an embodiment, the memory layers may include two terminal cells in a resistive memory (RRAM) a phase-change memory (PCRAM), a ferroelectric memory (FERAM), or a magnetic memory (MRAM).

"A security key may include portions with a first key portion disposed in a first area, and a second key portion disposed in a second area that is vertically located with respect to the first area. In such an embodiment, the first area may be a first memory layer, and the second area may be a second memory layer disposed over the first memory layer, wherein the second security key portion is used to unlock the first security key portion, and the first security key portion is used to unlock the logic layer. An embodiment may further comprise a third security key portion disposed on a third memory layer in a third area that is vertically located with respect to the first area.

"The present invention may be embodied on a system including a secure circuit device which includes a logic layer, one or more memory layers comprising non-volatile memory cells disposed over the logic layer and integrated with the logic layer in a monolithic structure, and a security key disposed in the non-volatile memory cells of at least one memory layer, the security key being a key required for enabling access to the logic layer for operation. The one or more memory layers may include a first memory layer and a second memory layer.

"In an embodiment, a security circuit in the system has security key that includes a first key portion disposed in a first area, and a second key portion disposed in a second area that is vertically located with respect to the first area. The first area may be a first memory layer, and the second area may be a second memory layer disposed over the first memory layer, wherein the second security key portion is used to unlock the first security key portion, and the first security key portion is used to unlock the logic layer. The circuit in the system may further include a third security key portion disposed on a third memory layer, wherein the first, second, and third security key portions are all needed to unlock the logic layer, and a dummy key disposed in one or more memory layer.

"In an embodiment of the system, the non-volatile memory cells storing the security key may be one time programmable memory cells, and in an embodiment they may include two terminal cells. The non-volatile memory cells may be resistive memory cells arranged in a crossbar configuration. The logic layer may include one or more processing or computational elements, and the system may further comprise access logic, wherein the access logic is configured to receive the security key disposed in the non-volatile memory cells and is configured to enable access to the logic layer in response thereto.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 illustrates a lower layer of an integrated circuit device according to an embodiment of the present invention.

"FIG. 2 illustrates a plurality of layers in an integrated circuit device according to an embodiment of the present invention.

"FIG. 3 illustrates a memory cell according to an embodiment of the present invention.

"FIGS. 4A and 4B illustrate electrical behavior of a memory cell according to an embodiment of the present invention.

"FIGS. 5A and 5B illustrate physical states of a memory cell according to an embodiment of the present invention.

"FIG. 6 illustrates a memory array according to an embodiment of the present invention.

"FIG. 7 illustrates a plurality of memory layers according to an embodiment of the present invention.

"FIGS. 8A to 8C illustrate memory and logic layers according to various embodiments of the present invention.

"FIG. 9 illustrates a computer system according to an embodiment of the present invention.

"FIG. 10 illustrates a packaged device according to an embodiment of the present invention.

"FIG. 11 illustrates a system on a chip according to an embodiment of the present invention."

For additional information on this patent application, see: MINASSIAN, George. Secure Circuit Integrated with Memory Layer. Filed November 9, 2012 and posted May 22, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=452&p=10&f=G&l=50&d=PG01&S1=20140515.PD.&OS=PD/20140515&RS=PD/20140515

Keywords for this news article include: Crossbar Inc.

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Source: Politics & Government Week


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