News Column

Patent Issued for Logic Coding in an Integrated Circuit

June 4, 2014



By a News Reporter-Staff News Editor at Journal of Engineering -- STMicroelectronics (Rousset) SAS (Rousset, FR) has been issued patent number 8730707, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventor is Fornara, Pascal (Pourrieres, FR).

This patent was filed on March 28, 2008 and was published online on May 20, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "The present invention generally relates to integrated circuits and, more specifically, to the non-volatile storage in an integrated circuit of a coding set on manufacturing of this circuit.

"An example of application of the present invention relates to non-volatile read-only memories (ROM). Another example relates to logic interconnects within an integrated circuit.

"In many cases, there is a need to definitively code, on manufacturing of the integrated circuit, digital words in a memory or logic states conditioning the circuit operation. For this purpose, a ROM-type memory in which the coding is performed by interconnecting the drain and source of transistors forming the memory cells is generally used, so that the state read from the cell depends on the presence of this connection. The first metallization level of the structure is generally used to perform this programming.

"A disadvantage of such a programming is that it is visible by analysis of the mask for forming the interconnection level, for example, by restoring of this mask from a circuit (reverse engineering)."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventor's summary information for this patent: "The present invention aims at overcoming all or part of the disadvantages of known solutions of logic state coding at the manufacturing of an integrated circuit.

"An object more specifically is the forming of a read-only memory.

"Another object is to make the logic state programming invisible by analysis of the mask for defining the interconnection levels of the structure.

"Another object aims at a solution compatible with current circuits for interpreting logic states and especially read-only memories.

"To achieve all or part of these objects, as well as others, an embodiment of the present invention provides a method for programming a read-only memory formed of MOS transistors, in which the programming is set by a mask for forming an insulating layer prior to the forming of contacts of active regions of the transistors.

"According to an embodiment, the lines for interconnecting several transistors in series in a first direction are formed, with a pattern independent from the programming, in said conductive level.

"According to an embodiment, said insulating layer is an oxide and nitride bilayer.

"The present invention also provides an interconnection structure between two logic levels of an integrated circuit, comprising, between an active region on a semiconductor substrate and a via connected to an upper conductive level, an insulating layer for masking a lack of interconnection.

"The present invention also provides a read-only memory cell formed of a MOS transistor, in which the programming state is set by the presence or not of an insulating layer between an active region and a conductive contact recovery via towards an upper conductive level.

"The present invention also provides a read-only memory.

"According to an embodiment, tracks for interconnecting drain and source contacts of the transistors in a first direction are uninterrupted.

"The foregoing and other objects, features, and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings."

For the URL and additional information on this patent, see: Fornara, Pascal. Logic Coding in an Integrated Circuit. U.S. Patent Number 8730707, filed March 28, 2008, and published online on May 20, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=56&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=2780&f=G&l=50&co1=AND&d=PTXT&s1=20140520.PD.&OS=ISD/20140520&RS=ISD/20140520

Keywords for this news article include: STMicroelectronics.

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Source: Journal of Engineering


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