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Researchers Submit Patent Application, "Semiconductor Devices with Enhanced Electromigration Performance", for Approval

June 4, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Gambino, Jeffrey P. (Westford, VT); Harame, David L. (Essex Junction, VT); Li, Baozhen (South Burlington, VT); Sullivan, Timothy D. (Underhill, VT); Zetterlund, Bjorn K. A. (Bolton, MA), filed on November 12, 2012, was made available online on May 22, 2014.

The patent's assignee is International Business Machines Corporation.

News editors obtained the following quote from the background information supplied by the inventors: "The demand for high performance in bipolar transistors requires a copper interconnect to carry high current density and also work at high temperatures. This places severe challenges on copper interconnect reliability, especially concerning electromigration issues. Electromigration decreases the reliability of integrated circuits (ICs), with eventual loss of connections or failure of the circuit. Also, with increasing miniaturization, the probability of failure due to electromigration increases in very-large-scale integration (VLSI) and ultra-large-scale integration (ULSI) circuits because both the power density and the current density increase. Thus, as the structure size in ICs decreases, the practical significance of the electromigration effect increases.

"In advanced semiconductor manufacturing processes, copper has replaced aluminum as the interconnect material of choice. Despite its greater fragility in the fabrication process, copper is intrinsically less susceptible to electromigration. However, electromigration continues to be an ever present challenge to device fabrication.

"Some research has lead to simply widening metal lines in order to address electromigration issues. However, this is not satisfactory, particularly for VSLI and ULSI circuits. For example, increasing metal line width can only increase the current carrying capability, linearly, while the high junction temperature degrades the current carrying capability exponentially. Furthermore, using metal lines much wider than the device contact will have current crowding issues and device density issues. Also, a high temperature gradient along the interconnect can cause thermal migration and stress migration problems.

"Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "In an aspect of the invention, a method comprises forming at least one metal line in electrical contact with a device. The method further comprises forming at least one staple structure in electrical contact with the at least one metal line. The at least one staple structure is formed such that electrical current passing through the at least one metal line also passes through the at least staple structure to reduce electromigration issues.

"In an aspect of the invention, a method of forming a structure comprises forming a last wiring layer in a dielectric layer, in electrical contact with a transistor formed in a lower layer of the structure. The method further comprises forming at least one via hole in the dielectric layer, exposing the last wiring layer. The method further comprises forming at least one trench in the dielectric layer and over the at least one via hole. The method further comprises lining the at least one via hole and the at least one trench with conductive liner material. The method further comprises filling the at least one via hole and the at least one trench with conductive material such that the at least one via hole forms at least one conductive via and the at least one trench forms a conductive bar structure in direct electrical contact with the at least one conductive via. Electrical current flowing in the last wiring layer can also flow through the at least one conductive via and the conductive bar structure to mitigate electromigration effects in the last wiring layer.

"In an aspect of the invention, a structure comprises a last metal line in electrical contact with an underlying device, and at least one staple structure in direct electrical contact with the last metal line. The at least one staple structure reduces electromigration issues in the last metal line.

"In another aspect of the invention, a design structure tangibly embodied in a machine readable storage medium for designing, manufacturing, or testing an integrated circuit is provided. The design structure comprises the structures of the present invention. In further embodiments, a hardware description language (HDL) design structure encoded on a machine-readable data storage medium comprises elements that when processed in a computer-aided design system generates a machine-executable representation of a hetero junction bipolar transistor with enhanced electromigration performance, which comprises the structures of the present invention. In still further embodiments, a method in a computer-aided design system is provided for generating a functional design model of the hetero junction bipolar transistor with enhanced electromigration performance. The method comprises generating a functional representation of the structural elements of the hetero junction bipolar transistor with enhanced electromigration performance.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

"The present invention is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present invention.

"FIG. 1a shows a side view of structures and respective processing steps in accordance with aspects of the present invention;

"FIG. 1b shows a top down view of the structures of FIG. 1a;

"FIG. 2 shows alternative arrangements of structures shown in FIGS. 1a and 1b, and respective processing steps in accordance with aspects of the present invention;

"FIG. 3 shows a structure and respective processing steps in accordance with additional aspects of the present invention;

"FIG. 4 shows a top down view of an alternative arrangement of structures and respective processing steps in accordance with aspects of the present invention;

"FIG. 5 shows structures and respective processing steps in accordance with additional aspects of the present invention;

"FIG. 6 shows a structure and respective processing steps in accordance with additional aspects of the present invention;

"FIG. 7 shows a hetero junction bipolar transistor with enhanced electromigration performance, implementing structures according to aspects of the present invention; and

"FIG. 8 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test."

For additional information on this patent application, see: Gambino, Jeffrey P.; Harame, David L.; Li, Baozhen; Sullivan, Timothy D.; Zetterlund, Bjorn K. A. Semiconductor Devices with Enhanced Electromigration Performance. Filed November 12, 2012 and posted May 22, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=5426&p=109&f=G&l=50&d=PG01&S1=20140515.PD.&OS=PD/20140515&RS=PD/20140515

Keywords for this news article include: Electronics, Semiconductor, International Business Machines Corporation.

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Source: Electronics Newsweekly


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