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Researchers Submit Patent Application, "Semiconductor Device Including an Asymmetric Feature, and Method of Making the Same", for Approval

June 4, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Chang, Josephine (Mahopac, NY); Lauer, Isaac (Mahopac, NY); Lin, Chung-Hsun (White Plains, NY); Sleight, Jeffrey (Ridgefield, CT), filed on January 17, 2014, was made available online on May 22, 2014.

The patent's assignee is International Business Machines Corporation.

News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates to a semiconductor device (and method of making the device) and more particularly, a semiconductor device which includes first and second contacts, the first contact being asymmetric with respect to the second contact.

"FIG. 7 illustrates a conventional semiconductor device 700 (e.g., field effect transistor (FET)). As illustrated in FIG. 7, the conventional device includes a gate 710, source and drain regions 730a, 730b, and contact layers 740a, 740b. As illustrated in FIG. 7 the source and drain regions 730a, 730b conventionally have the same width and depth (e.g., same volume) and are formed of the same material (e.g., the same doped semiconductor material).

"In addition, as further illustrated in FIG. 7, the contact layers 740a, 740b conventionally have the same width and height (e.g., volume), and are formed the same distance away from the gate of the FET. In addition, the contact layers 740a, 740b are typically formed of the same material.

"The contact layers 740a, 740b are layers of conductive material which are used to electrically connect features in conventional semiconductor devices. For example, in the conventional device 700, the first contact layer 740a may be used to contact the source region 730a, and the second contact layer 740b may be used to contact the drain region 730b.

"The contact layers 740a, 740b may be formed as stressed contact layers which may apply a tensile or compressive stress on the underlying substrate. For example, in the example above, the first contact layer 740a may apply a stress to the source region 730a and the second contact layer 740b may be apply a stress to the drain region 740b.

"The use of stressed contact layers to enhance device (e.g., field effect transistor (FET)) performance is becoming pervasive in advanced silicon complementary metal oxide semiconductor (CMOS) devices.

"As pitch is further scaled, the amount of benefit incorporated (e.g., by the use of stressed contact layers) is a complex function of the contact material, contact size, and distance of the contact from the device."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "In view of the foregoing and other problems, disadvantages, and drawbacks of the aforementioned conventional systems and methods, an exemplary aspect of the present invention is directed to an asymmetric contact device and a method of making the device.

"An exemplary aspect of the present invention is directed a semiconductor device (e.g., field effect transistor (FET)) having an asymmetric feature. The semiconductor device includes a first gate formed on a substrate, first and second diffusion regions formed in the substrate on a side of the first gate, and first and second contacts which contact the first and second diffusion regions, respectively, the first contact being asymmetric with respect to the second contact.

"Another exemplary aspect of the present invention is directed to a semiconductor device including an asymmetric feature. The device includes a first FET including a first gate formed on a substrate; first and second diffusion regions formed in the substrate on a side of the first gate; and first and second contacts which contact the first and second diffusion regions, respectively, the first contact being asymmetric with respect to the second contact. The device also includes a second FET formed on the substrate adjacent to the first FET and including a second gate formed on the substrate, third and fourth diffusion regions formed in the substrate on a side of the second gate, and third and fourth contacts which contact the third and fourth diffusion regions, respectively, and a third FET formed on the substrate adjacent to the second FET, the third FET including a third gate formed on the substrate, fifth and sixth diffusion regions formed in the substrate on a side of the third gate, and fifth and sixth contacts which contact the fifth and sixth diffusion regions, respectively. Further, a pitch between the first and second gates includes a first pitch and a pitch between the second and third gates includes a second pitch which is different from the first pitch, and the asymmetry of the first and second contacts includes one of the first contact is located a first distance from the first gate, and the second contact is located a second distance from the first gate, the second distance being different than the first distance, the first contact includes a first volume, and the second contact includes a second volume, the second volume being different than the first volume, the first contact includes a first material, and the second contact includes a second material, the second material being different than the first material, and the first contact includes one of a stressed and unstressed contact, and the second contact includes the other one of the stressed and unstressed contact.

"Another exemplary aspect of the present invention is directed to a method of making a semiconductor device. The method includes forming a first gate a substrate, forming first and second diffusion regions in the substrate on a side of the first gate, and forming first and second contacts which contact the first and second diffusion regions, respectively, the first contact being asymmetric with respect to the second contact.

"Another exemplary aspect of the present invention is directed to a method of making a semiconductor device, the method includes forming first, second and third field effect transistors (FETs) on a substrate, the first, second and third FETs including first, second and third gates, respectively, such that a pitch between the first and second gates includes a first pitch and a pitch between the second and third gates includes a second pitch which is different than the first pitch, by one of a first process of using a mask to lithographically define the second gate adjacent to the first gate on the substrate, and the third gate adjacent to the second gate on the substrate, such that the second pitch is different than the first pitch, a second process of, using a mask to lithographically define a plurality of gates including the second gate adjacent to the first gate on the substrate, the third gate adjacent to the second gate on the substrate, and an intermediate gate between the first and second gates on the substrate, a pitch between the plurality of gates including the same pitch, and removing the intermediate gate such that the second pitch is different than the first pitch, and a third process of using a mask to lithographically define a second gate adjacent to the first gate on the substrate, such that the second gate has a channel length which is less than a channel length of the first gate.

"With its unique and novel features, the present invention may provide a manner of achieving different drive strengths in a semiconductor device (e.g., a field effect transistor device) without (or in addition to) the use of channel doping.

BRIEF DESCRIPTION OF THE DRAWINGS

"The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of the embodiments of the invention with reference to the drawings, in which:

"FIG. 1A illustrates a semiconductor device 100, according to the exemplary aspects of the present invention;

"FIG. 1B illustrates a semiconductor device 150, according to the exemplary aspects of the present invention;

"FIG. 1C illustrates a semiconductor device 160, according to the exemplary aspects of the present invention;

"FIG. 1D illustrates a semiconductor device 170, according to the exemplary aspects of the present invention;

"FIG. 1E illustrates a semiconductor device 180, according to the exemplary aspects of the present invention;

"FIG. 1F illustrates a semiconductor device 190, according to the exemplary aspects of the present invention;

"FIG. 1G illustrates a semiconductor device 195, according to the exemplary aspects of the present invention;

"FIG. 2A illustrates a semiconductor device 200, according to the exemplary aspects of the present invention;

"FIG. 2B illustrates a semiconductor device 250, according to the exemplary aspects of the present invention;

"FIG. 3 illustrates a method 300 of making a semiconductor device, according to the exemplary aspects of the present invention;

"FIG. 4A illustrates a method 400 of making a semiconductor device (e.g., forming gates 410a, 410b and 410c), according to the exemplary aspects of the present invention;

"FIG. 4B illustrates a method 400 of making a semiconductor device (e.g., forming diffusion regions 430a, 430b), according to the exemplary aspects of the present invention;

"FIG. 4C illustrates a method 400 of making a semiconductor device (e.g., forming contacts 440a, 440b and 440c), according to the exemplary aspects of the present invention;

"FIG. 5A illustrates a method 500 of making a semiconductor device (e.g., forming gates 510a, 510b and 510c), according to the exemplary aspects of the present invention; and

"FIG. 5B illustrates a method 500 of making a semiconductor device (e.g., forming diffusion regions 530a, 530b), according to the exemplary aspects of the present invention; and

"FIG. 5C illustrates a method 500 of making a semiconductor device (e.g., forming contacts 540a, 540b and 540c), according to the exemplary aspects of the present invention; and

"FIG. 6A illustrates a method 600 of making a semiconductor device (e.g., forming gates 610a, 610b, 610i and 610c), according to the exemplary aspects of the present invention;

"FIG. 6B illustrates a method 600 of making a semiconductor device (e.g., removing gate 610i), according to the exemplary aspects of the present invention;

"FIG. 6C illustrates a method 600 of making a semiconductor device (e.g., forming diffusion regions 630a, 630b), according to the exemplary aspects of the present invention;

"FIG. 6D illustrates a method 600 of making a semiconductor device (e.g., forming contacts 640a, 640b and 640c), according to the exemplary aspects of the present invention; and

"FIG. 7 illustrates a conventional semiconductor device 700."

For additional information on this patent application, see: Chang, Josephine; Lauer, Isaac; Lin, Chung-Hsun; Sleight, Jeffrey. Semiconductor Device Including an Asymmetric Feature, and Method of Making the Same. Filed January 17, 2014 and posted May 22, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=5596&p=112&f=G&l=50&d=PG01&S1=20140515.PD.&OS=PD/20140515&RS=PD/20140515

Keywords for this news article include: Electronics, Semiconductor, International Business Machines Corporation.

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Source: Electronics Newsweekly


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