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Patent Issued for Synchronization, Re-Synchronization, Addressing, and Serialized Signal Processing for Daisy-Chained Communication Devices

June 4, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Pan, Yang (Shanghai, CN); Josefsson, Olafur M. (Hafnarfjordur, IS); Yan, Dongqin (Shanghai, CN); Huin, Camille L. C. J. (Andover, MA), filed on March 22, 2012, was published online on May 20, 2014.

The assignee for this patent, patent number 8731002, is Invensense, Inc. (San Jose, CA).

Reporters obtained the following quote from the background information supplied by the inventors: "In certain communication systems, multiple devices transmit data to a controller via a communication channel (e.g., a single-wire bus) that is logically divided into a number of successive time slots, with each time slot having a predetermined number of bits. Each device transmits data to the controller in one or more designated time slots according to a slot allocation scheme, which is fixed in some communication systems and variable in other communication systems. Often times, the devices transmit at fixed regular intervals, and therefore the communication channel is often logically divided into a number of frames with each frame containing a predetermined number of time slots, and each device transmits in its respective time slot(s) in each frame. Thus, for example, a first device may transmit in the first time slot of each frame, a second device may transmit in the second time slot of each frame, and so on. In some systems, devices may transmit in multiple time slots, for example, a first device may transmit in the first and second time slots of each frame, a second device may transmit in the third and fourth time slots of each frame, and so on. In some systems, different devices may transmit in different numbers of time slots, for example, a first device may transmit in the first time slot of each frame, a second device may transmit in the second and third time slots of each frame, a third device may transmit in the fourth time slot of each frame, and so on.

"For convenience, N will be used herein to represent the number of time slots per frame, B will be used herein to represent the number of bits per time slot, and M will be used herein to represent the number of devices. A particular embodiment might have, for example, eight 32-bit slots per frame (i.e., N=8, B=32), although the present invention is not limited to any particular values of N and B. The actual data transmitted in each time slot may use all B bits or may use fewer than all B bits (e.g., a 24-bit sample of digital audio may be conveyed in a 32-bit time slot). In various systems, there may be a one-to-one relationship between SCK and bits (e.g., one cycle of SCK for each bit) or there may be other relationships between SCK and bits (e.g., two or more cycles of SCK for each bit).

"FIG. 1 schematically shows an exemplary system having a number of devices 1041-104M that transmit data to controller 102 in a TDM fashion, as known in the art. In this exemplary configuration, the controller acts as a bus master and all of the slaves operate as slave devices. The controller 102 provides a clock signal (SCK) and a frame synchronization signal (WS) to all of the devices 104. The controller 102 also sends commands to the devices 104 (e.g., based on a unique address for each device 104) over one or more command lines, for example, to configure the time slot(s) for each device 104 to transmit data over the data line (SD). Based on the SCK and FS signals, and the configuration information provided by the controller 102, each device 104 transmits in one or more designated time slots on the SD line.

"FIG. 2 schematically shows another exemplary system having a number of devices 2041-204M that transmit data to controller 202 in a TDM fashion, as known in the art. In this exemplary system (which is similar to configurations shown and described in United States Publication US 2008/0069151 entitled 'Variable Time Division Multiplex Transmission System' and filed by Satoh et al., which is hereby incorporated herein by reference in its entirety), each of the devices 204 includes both master operating logic and slave operating logic, and the operational mode of each device 204 may be set, for example, using a hardware pin on the device. In this exemplary embodiment, the first device 2041 is set to operate as the bus master (e.g., via the M/S pin) and provides a clock signal to both the controller 202 and the other devices 204, which are set to operate as slave devices (e.g., via the respective M/S pin). The device 2041 also provides a frame synchronization signal to the controller 202 to mark the start of each frame and provides a delayed synchronization signal to the second device 2042 in the chain to mark the start of that device's time slot(s). Each slave device in the chain, beginning with the second device 2042, provides a delayed frame synchronization signal to the next successive device in the chain.

"A similar system is shown and described in Low-Power, Highly-Integrated, Programmable 16-Bit, 26-KSPS, Dual-Channel CODEC (Texas Instruments, Revised April 2005), which is hereby incorporated herein by reference in its entirety. Specifically, FIG. 20 of this document shows a number of devices in a cascade connection, where the first device in the cascade is configured as a master device and both the DSP and the remaining devices in the cascade operate as slaves of the master device. Each slave device is configured to provide a delayed frame synchronization signal to the next successive slave device, and the devices are capable of automatically determining the number of devices in the cascade and automatically assigning addresses to the devices. One issue with such a configuration is that all of the devices carry both master and slave logic, with the master/slave operation of the device selected by the M/S pin. Among other things, the ability of each device to operate as a master or slave adds cost and complexity to each device."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "In certain embodiments, a time-division multiplexed communication system includes a data line, a controller, and at least one slave device in communication with the controller. The controller includes a clock output for providing a clock signal, a frame sync output for providing a frame sync signal indicating the beginning of each of a number of successive frames, and a data pin coupled to the data line. Each slave-only device includes a clock input coupled to the clock output of the controller for receiving the clock signal, a data pin coupled to the data line, a frame sync input, and a frame sync output. The controller and the at least one slave-only device are interconnected in a chain configuration beginning with the controller, wherein the frame sync input of each slave-only device is coupled to the frame sync output of the previous device in the chain, and wherein the controller provides the frame sync signal on its frame sync output. Each slave-only device is configured to perform an auto-initialization process including monitoring the frame sync input for frame sync signals and after receiving at least two frame sync signals on the frame sync input, generating an inner frame clock based on a plurality of the received frame sync signals and synchronized with the frame sync signal provided on the controller frame sync output, outputting the inner frame clock on the frame sync output, and entering a data passing mode, including generating an internal operational clock based on the inner frame clock.

"In various alternative embodiments, generating the inner frame clock may involve determining the number of clock signal cycles in a frame based on the clock signal and the plurality of frame sync signals, and generating the internal operational clock may involve generating the internal operational clock based on the inner frame clock and the number of clock signal cycles in a frame.

"In other alternative embodiments, the chain configuration may include a plurality of slave-only devices. In some embodiments, all of the slave-only devices may be configured to access the same number of time slots per frame. In other embodiments, two or more slave-only devices may be configured to access different numbers of time slots per frame. In some embodiments, all of the slave-only devices may be the same type of device. In other embodiments, two or more slave-only devices may be different types of devices. In certain embodiments, at least one of the slave-only devices may include a MEMS microphone device.

"In yet other alternative embodiments, each slave-only device may be configured to determine a maximum number of slave-only devices supported by the controller based on the clock signal and the frame sync signal. Furthermore, the data pin of each slave-only device may include a programmable driver, and each slave-only device may be configured to program a power setting of the programmable driver based on the maximum number of slave-only devices supported by the controller. The data pin of each slave-only device may be configured or configurable for transmitting data via the data line or receiving data from the data line.

"Additional embodiments include apparatus comprising at least one slave-only device for operation in a time-division multiplexed communication system having a controller in communication with the at least one slave-only device, where each slave-only device includes a clock input for receiving a clock signal, a frame sync input for receiving a frame sync signal indicating the start of each of a number of successive frames, a frame sync output for outputting a delayed frame sync signal, and a slave-only TDM bus interface coupled to the clock input, the frame sync input, and the frame sync output and including a data pin for coupling to a data line. The TDM bus interface is configured to perform an auto-initialization process including monitoring the frame sync input for frame sync signals and after receiving at least two frame sync signals on the frame sync input, generating an inner frame clock based on a plurality of the received frame sync signals and synchronized with a frame sync signal provided on a controller frame sync output, outputting the inner frame clock on the frame sync output, and entering a data passing mode, including generating an internal operational clock based on the inner frame clock.

"In various alternative embodiments, the TDM bus interface may be configured to determine the number of clock signal cycles in a frame based on the clock signal and the plurality of frame sync signals, and the TDM bus interface may be further configured to generate the internal operational clock based on the inner frame clock and the number of clock signal cycles in a frame.

"In other alternative embodiments, the TDM bus interface may be further configured to determine a maximum number of slave-only devices that can be supported in a chain based on the clock signal and the frame sync signal received on the frame sync input. Furthermore, the data pin may include a programmable driver, and the TDM bus interface may be further configured to program a power setting of the programmable driver based on the maximum number of slave-only devices. The data pin may be configured or configurable for at least one of transmitting data via the data line or receiving data from the data line.

"In other alternative embodiments, the apparatus may include a plurality of slave-only devices integrated onto a single chip. In some embodiments, the controller may be integrated with the plurality of slave-only devices onto the single chip. In some embodiments, a digital MEMS microphone may be coupled to the slave-only TDM bus interface.

"Additional embodiments include a method for automatically initializing a slave-only device in a time-division multiplexed communication system having a controller in communication with at least one slave-only device, wherein data is transmitted in successive frames, each frame including a predetermined number of time slots. The method involves monitoring, by a TDM interface of the slave-only device, a frame sync input of the slave-only device for frame sync signals; and after receiving at least two frame sync signals on the frame sync input, generating an inner frame clock for the slave-only device based on a plurality of the received frame sync signals and synchronized with a frame sync signal output by the controller, outputting the inner frame clock on a frame sync output of the slave-only device, and entering a data passing mode, including generating an internal operational clock for the slave-only device based on the inner frame clock.

"In various alternative embodiments, generating the internal operational clock may involve receiving a clock signal from the controller via a clock input of the slave device, determining the number of clock signal cycles in a frame based on clock signal and the plurality of frame sync signals, and generating the internal operational clock based on the inner frame clock and the number of clock signal cycles in a frame. The method may further involve determining a maximum number of slave-only devices based on the clock signal and the frame sync signal. The slave-only device may include a programmable driver for the data output, and the method may further involve programming the programmable driver based on the maximum number of slave-only devices. The slave-only device may include an analog-to-digital transducer or digital-to-analog transducer, and the method may further involve providing the internal frame clock to the transducer. The transducer may include a microphone that produces digital audio samples.

"Additional embodiments may be disclosed and claimed."

For more information, see this patent: Pan, Yang; Josefsson, Olafur M.; Yan, Dongqin; Huin, Camille L. C. J.. Synchronization, Re-Synchronization, Addressing, and Serialized Signal Processing for Daisy-Chained Communication Devices. U.S. Patent Number 8731002, filed March 22, 2012, and published online on May 20, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=50&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=2486&f=G&l=50&co1=AND&d=PTXT&s1=20140520.PD.&OS=ISD/20140520&RS=ISD/20140520

Keywords for this news article include: Electronics, Invensense Inc., Signal Processing.

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Source: Electronics Newsweekly


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