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Patent Issued for Self-Aligned Trench Field Effect Transistors with Regrown Gates and Bipolar Junction Transistors with Regrown Base Contact Regions...

June 4, 2014



Patent Issued for Self-Aligned Trench Field Effect Transistors with Regrown Gates and Bipolar Junction Transistors with Regrown Base Contact Regions and Methods of Making

By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Merrett, Joseph Neil (Xenia, OH); Sankin, Igor (Perrysburg, OH), filed on August 14, 2012, was published online on May 20, 2014.

The patent's assignee for patent number 8729628 is Power Integrations, Inc. (San Jose, CA).

News editors obtained the following quote from the background information supplied by the inventors: "This application relates generally to the field of semiconductor power devices designed for high speed, high power applications and, in particular, to the manufacture of field-effect transistors (FETs) having vertical channels and regrown p-n junction gates and to bipolar junction transistors (BJTs) with regrown base contact regions.

"A field-effect transistor (FET) is a type of transistor commonly used for weak-signal amplification (e.g., for amplifying wireless signals). The device can amplify analog or digital signals. It can also switch DC or function as an oscillator. In the FET, current flows along a semiconductor path called the channel. At one end of the channel, there is an electrode called the source. At the other end of the channel, there is an electrode called the drain. The physical diameter of the channel is fixed, but its effective electrical diameter can be varied by the application of a voltage to a control electrode called the gate. The conductivity of the FET depends, at any given instant in time, on the electrical diameter of the channel. A small change in gate voltage can cause a large variation in the current from the source to the drain. This is how the FET amplifies signals.

"The gate of an FET can be a metal-semiconductor Schottky barrier (MESFET), a p-n junction (JFET), or a metal-oxide-semiconductor gate (MOSFET). The p-n junction FET (JFET) has a channel of N-type semiconductor (N-channel) or P-type semiconductor (P-channel) material and a gate of semiconductor material of the opposite semiconductor type on the channel. The Metal-Semiconductor-Field-Effect-Transistor (MESFET) has a channel of N-type or P-type semiconductor material and a Schottky metal gate on the channel.

"Bipolar junction transistors (BJTs) are semiconductor devices having two back-to-back PN junctions. BJTs have a thin and typically lightly doped central region known as the base (B) having majority charge carriers of opposite polarity to those in the surrounding material. The two outer regions of the device are known as the emitter (E) and the collector (C). Under the proper operating conditions, the emitter injects majority charge carriers into the base region. Because the base is thin, most of these charge carriers will ultimately reach the collector. The emitter is typically highly doped to reduce resistance and the collector is typically lightly doped to reduce the junction capacitance of the collector-base junction.

"Semiconductor devices such as FETs and BJTs are typically made using ion implantation techniques. Ion implantation, however, requires high temperature post implant anneals which increases the time required to manufacture the device and which can result in damage to the device.

"Accordingly, there still exists a need for improved methods of making semiconductor devices such as FETs and BJTs."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "According to a first embodiment, a method of making a semiconductor device is provided which comprises:

"disposing a mask on an upper surface of a source/emitter layer of semiconductor material of a first conductivity type, wherein the source/emitter layer is on a channel layer of semiconductor material of the first conductivity type or a base layer of semiconductor material of a second conductivity type different than the first conductivity type, wherein the channel or base layer is on a drift layer of semiconductor material of the first conductivity type and wherein the drift layer is on a semiconductor substrate layer;

"selectively etching through the source/emitter layer and into the underlying channel or base layer through openings in the mask to form one or more etched features having bottom surfaces and sidewalls;

"epitaxially growing semiconductor material of the second conductivity type on the bottom surfaces and sidewalls of the etched features through openings in the mask to form gate regions/base contact regions, wherein the mask inhibits growth on the masked upper surface of the source/emitter layer;

"subsequently filling the etched features with a planarizing material;

"etching the gate regions/base contact regions until the gate regions/base contact regions no longer contact the source/emitter layer; and

"removing mask and planarizing material remaining after etching the gate regions/base contact regions.

"According to a second embodiment, a method of making a semiconductor device is provided which comprises:

"disposing an etch mask on an upper surface of a source/emitter layer of semiconductor material of a first conductivity type, wherein the source/emitter layer is on a channel layer of semiconductor material of the first conductivity type or a base layer of semiconductor material of a second conductivity type different than the first conductivity type, wherein the channel or base layer is on a drift layer of semiconductor material of the first conductivity type and wherein the drift layer is on a semiconductor substrate layer;

"selectively etching through the source/emitter layer and into the underlying channel or base layer through openings in the etch mask to form one or more etched features having bottom surfaces and sidewalls;

"removing the etch mask to expose the upper surface of the source/emitter layer;

"epitaxially growing a gate layer/base contact layer of semiconductor material of the second conductivity type on the upper surface of the source/emitter layer and on the bottom surfaces and sidewalls of the etched features;

"subsequently filling the etched features with a first planarizing material;

"etching through the gate layer/base contact layer on the upper surface of the source/emitter layer to expose underlying source/emitter layer;

"removing first planarizing material remaining after etching through the gate layer/base contact layer;

"anisotropically depositing a dry etch mask material on the upper surface of the source/emitter layer and on bottom surfaces of the etched features;

"etching the dry etch mask material to expose gate layer/base contact layer on the sidewalls of the etched features adjacent the upper surface of the source/emitter layer;

"filling the etched features with a second planarizing material such that the gate layer/base contact layer adjacent the source/emitter layer on the sidewalls of the etched features is exposed;

"etching through exposed gate layer/base contact layer on the sidewalls of the etched features adjacent the source/emitter layer to expose underlying source/emitter layer until the gate layer/base contact layer remaining in the etched features no longer contacts the source/emitter layer; and

"removing dry etch mask material and second planarizing material remaining after etching through exposed gate layer/base contact layer on the sidewalls of the etched features.

"According to a third embodiment, a method of making a semiconductor device is provided which comprises:

"disposing an etch mask on an upper surface of a channel layer of semiconductor material of a first conductivity type or a base layer of semiconductor material of a second conductivity type different than the first conductivity type, wherein the channel or base layer is on a drift layer of semiconductor material of the first conductivity type and wherein the drift layer is on a semiconductor substrate layer;

"selectively etching the channel or base layer through openings in the mask to form one or more etched features having bottom surfaces and sidewalls;

"removing the etch mask to expose the upper surface of the channel or base layer;

"epitaxially growing a gate layer/base contact layer of semiconductor material of the second conductivity type on the upper surface of the channel or base layer and on the bottom surfaces and sidewalls of the etched features;

"subsequently filling the etched features with a first planarizing material;

"etching through the gate layer/base contact layer on the upper surface of the channel or base layer such that gate layer/base contact layer remains on the bottom surfaces and sidewalls of the etched features;

"removing first planarizing material remaining after etching through the gate layer/base contact layer;

"depositing a regrowth mask layer on the upper surface of the channel or base layer and on the gate layer/base contact layer on the bottom surfaces and sidewalls of the etched features;

"subsequently filling the etched features with a second planarizing material;

"etching through the regrowth mask layer on the upper surface of the channel or base layer to expose underlying channel or base layer, wherein regrowth mask layer remains on the gate layer/base contact layer on the bottom surfaces and sidewalls of the etched features;

"removing second planarizing material remaining after etching through the regrowth mask layer;

"epitaxially growing a first layer of semiconductor material of the first conductivity type on the upper surface of the channel or base layer, wherein the regrowth mask layer remaining on the gate layer/base contact layer on the bottom surfaces and sidewalls of the etched features inhibits growth of the first layer of semiconductor material of the first conductivity type;

"epitaxially growing a second layer of semiconductor material of the first conductivity type on the first layer of semiconductor material of the first conductivity type, wherein the regrowth mask layer remaining on the gate layer/base contact layer on the bottom surfaces and sidewalls of the etched features inhibits growth of the second layer of semiconductor material of the first conductivity type; and

"removing remaining regrowth mask layer.

"According to a fourth embodiment, a method of making a semiconductor device is provided which comprises:

"disposing an etch mask on an upper surface of a source/emitter layer of semiconductor material of a first conductivity type, wherein the source/emitter layer is on a channel layer of semiconductor material of the first conductivity type or a base layer of semiconductor material of a second conductivity type different than the first conductivity type, wherein the channel or base layer is on a drift layer of semiconductor material of the first conductivity type and wherein the drift layer is on a semiconductor substrate layer;

"selectively etching through the source/emitter layer and into the underlying channel or base layer through openings in the etch mask to form one or more etched features having bottom surfaces and sidewalls;

"removing the etch mask to expose the upper surface of the source/emitter layer;

"epitaxially growing a gate layer/base contact layer of semiconductor material of the second conductivity type on the upper surface of the source/emitter layer and on the bottom surfaces and sidewalls of the etched features;

"subsequently filling the etched features with a planarizing material;

"etching through the gate layer/base contact layer on the upper surface of the source/emitter layer and on the sidewalls of the etched features in contact with the source/emitter layer until the gate layer/base contact layer no longer contacts the source/emitter layer, wherein gate layer/base contact layer remains on the bottom surfaces of the etched features and on the sidewalls of the etched features in contact with the channel or base layer; and

"removing planarizing material remaining after etching through the gate layer/base contact layer.

"According to a fifth embodiment, a method of making a semiconductor device is provided which comprises:

"disposing an etch/regrowth mask on an upper surface of a source/emitter layer of semiconductor material of a first conductivity type, wherein the source/emitter layer is on a channel layer of semiconductor material of the first conductivity type or a base layer of semiconductor material of a second conductivity type different than the first conductivity type, wherein the channel or base layer is on a drift layer of semiconductor material of the first conductivity type and wherein the drift layer is on a semiconductor substrate layer;

"selectively etching through the source/emitter layer and into the underlying channel or base layer through openings in the mask to form one or more etched features having bottom surfaces and sidewalls;

"epitaxially growing semiconductor material of the second conductivity type on the bottom surfaces and sidewalls of the etched features through openings in the mask to form gate regions/base contact regions, wherein the mask inhibits growth on the masked upper surface of the source/emitter layer;

"optionally removing the mask to expose the upper surface of the source/emitter layer;

"depositing a dry etch mask material on bottom surfaces of the etched features and on either the upper surface of the source/emitter layer or on the mask;

"etching the dry etch mask material to expose upper portions of the gate regions/base contact regions on the sidewalls of the etched features;

"filling the etched features with a planarizing material such that the upper portions of the gate regions/base contact regions on the sidewalls of the etched features remain exposed;

"etching through exposed gate layer/base contact layer on the sidewalls of the etched features adjacent the source/emitter layer to expose underlying source/emitter layer until the gate layer/base contact layer remaining in the etched features no longer contacts the source/emitter layer; and

"removing etch/regrowth mask and planarizing material remaining after etching through exposed gate layer/base contact layer on the sidewalls of the etched features."

For additional information on this patent, see: Merrett, Joseph Neil; Sankin, Igor. Self-Aligned Trench Field Effect Transistors with Regrown Gates and Bipolar Junction Transistors with Regrown Base Contact Regions and Methods of Making. U.S. Patent Number 8729628, filed August 14, 2012, and published online on May 20, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=78&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=3854&f=G&l=50&co1=AND&d=PTXT&s1=20140520.PD.&OS=ISD/20140520&RS=ISD/20140520

Keywords for this news article include: Electronics, Semiconductor, Power Integrations Inc..

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Source: Electronics Newsweekly


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