Patent number 8730721 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "This disclosure relates generally to methods and apparatus for reducing or eliminating certain data errors associated with FLASH memory devices utilizing a NAND architecture.
"In general, a FLASH memory device is one type of memory device that can retain stored digital data, even when no power is being provided to the device.
"Typical FLASH memory devices are formed from a number of individual storage elements, where each storage element comprises a memory cell that includes a transistor and a charge storage area. In many FLASH devices, the charge storage area comprises either a floating gate or a charge-trapping region. The presence or absence of an electric charge in the charge storage area of a cell can be used to store a logic '1' or a logic '0' in the cell.
"For many FLASH memory devices, the presence of a relatively large electrical charge on the cell corresponds to a logic '1' and the absence of such a charge corresponds to a logic '0.' It should be noted, however, that this assignment of a logic '1' to the condition where charge is present is somewhat arbitrary and the presence of a charge could be used to indicate a logic '0' and the absence of charge as a logic '1.' For purposes of this disclosure, however, it will be presumed that the presence of charge corresponds to a logic '1' condition and the absence of charge to a logic '0.'
"The previous discussion of flash memory suggested the ability to store one of two logical states within a flash memory cell, a logical '0' or a logical '1'. While this is true of SLC (single-level cell) flash memory,
"The presence or absence of the charge in the associated storage cell may be stored and/or detected in a variety of ways. Certain FLASH memory devices utilize a NAND architecture ('NAND FLASH memory devices') to store and read the digital data stored within the memory cells of the device. A NAND architecture is one in which several FLASH memory cells are connected to one another in series.
"FIG. 1 generally illustrates a highly simplified NAND FLASH memory 100. FIG. 1 will be used to describe certain relevant aspects of the general operation of a NAND FLASH memory device.
"In the example of FIG. 1, the NAND FLASH memory 100 includes nine memory cells 110a-110i, arranged in a three-by-three array.
"For purposes of illustration, cells using a floating gate construction are used. In a floating gate transistor cell, it is common to identify a floating gate and a control gate, although other names may be used to describe these elements. The floating gate is generally electrically isolated from other transistor structures and is used to store electrical charge injected into it through a programming operation. The control gate is use to control the reading, writing (programming) and erasing of cells. Throughout this document, the term 'gate', without any modifiers, is understood to refer to the control gate.
"From top to bottom, the cells are coupled together in series to form what is sometimes called a bit line. As one example, cells 110a, 110d and 110g are coupled together in series to form a bit line. In the simplified illustrated example, a pull-up resistor is provided for each bit line. In an actual embodiment addressing circuitry, control transistors and other structures would be included. These elements are not illustrated in FIG. 1, which provides a highly simplified representation of a NAND FLASH memory.
"Across the structure, the gates of cells sharing the same relative location are connected to one another. Thus, the gates of cells 110d, 110e, and 110f are coupled to one another. The coupling of these gates of the cell is such that all of the cells sharing a common gate line are typically read from or written to at the same time.
"Typically, the memory cells within a NAND FLASH memory device are arranged into 'Pages' and 'Blocks.' A Page is a group of data bits that are accessed, internal to the memory, generally in a parallel manner at the same time. Thus, in the example of FIG. 1, the cells 110d, 110e, and 110f could be considered to be a Page, in the sense that the gates of the three cells are coupled to one another such that the data within the three cells can be accessed at the same time. Like FIG. 1, most NAND FLASH memory devices perform read or write operations on a Page-by-Page basis.
"While some flash memory devices support operations on 'partial pages', these partial page operations are generally less efficient than their complete page counterparts. The underlying physical mechanisms associated with these partial page operations are roughly identical to their complete page counterparts, except for the fact that they operate on a subset of the overall FLASH memory page. As such, even though such pages may be referred to in some situations as 'partial pages' because they are accessed in a parallel manner at the same time, they are considered 'pages' for purposes of this disclosure. As noted above, as used herein a 'Page' refers to a group of data bits within a given memory device that are accessed at the same time.
"In a NAND FLASH memory, the Pages of data within the memory may be arranged so that they are associated with one another in one or more 'Blocks' of data, typically as a result of the physical layout of the specific FLASH device at issue. In the example of FIG. 1, the grouping of the nine depicted memory cells 110a-110i could be considered to be a 'Block' of data.
"The exemplary device of FIG. 1 is highly simplified for purposes of discussion. Most actual FLASH memory devices will contain a substantially larger number of Pages and memory cells. For example, in current FLASH memory devices, the sizes of the Pages can vary from 512, 2,048, 4,096, or 8,192 bytes and the Blocks for a given FLASH device can vary in size, for example, from 32 Pages of 512 Bytes per Page for a 16 KB Block size; to 64 Pages of 2,048 bytes for a 128 KB Block size; to 64 Pages of 4,096 bytes for a 256 KB Block size; to 128 Pages of 4,096 bytes for a 512 KB Block size. The invention described herein does not presume a particular page size or architecture, beyond the architectural features leading to the read disturbance phenomenon described below.
"In general, there are a number of operations that are performed within FLASH memory devices. The most common such operations are the ERASE, PROGRAM, and READ operations. During an ERASE operation, the logical bit stored in a given memory cell is set to a logical '0,' which--in the example of discussion--corresponds to the absence of a substantial electric charge in the memory cell's charge storage area. The ERASE operation is typically performed by taking the voltage of the gates for the various storage devices within a Block, and other voltages that impact the amount of charge in the charge storage regions of the storage cells, to such levels that the electrical charge stored on the floating gates of the devices (or the charge trapping area) is reduced to zero or a low amount.
"Because of the physical nature of most NAND FLASH memory devices, the ERASE operation is performed on a 'Block' basis. Thus, anytime one desires to erase the data in a given memory cell within a given Block, one will also erase the data in all other memory cells within that Block.
"After a Block of FLASH memory is erased, the individual data within the device can be programmed. The PROGRAM operation involves the writing of data into a memory cell that has been previously ERASED. When one desires to write a logical '1' into a previously erased FLASH memory cell--which would have no or low stored charge and therefore be at a logic '0' level--one may use the PROGRAM operation to inject charge onto the floating gates of the erased cells (or into their charge trapping regions) at levels sufficient to alter their threshold voltages. The threshold voltage reflects, in a general sense, the value of control gate voltage required to turn the transistor on (conducting) or off (non-conducting). The PROGRAM operation is typically performed by driving the control gate voltage level of the cell to be programmed to a sufficiently high level, while maintaining the voltage levels for the other terminals of the transistor in the cell at levels sufficient for charge injection to occur. When one desires to write a logical '0' into a previously erased FLASH memory cell, the PROGRAM operation involves the maintenance of the state of the cell established during the ERASE operation. The PROGRAM operation is performed in such a way that all of the bits being programmed (typically all of the bits within a single Page) will be programmed to have the desired '1' or '0' levels at the same time.
"Once Pages of a FLASH memory device are programmed, they can be read. In general, the READ operation involves the reading of the logical data stored in the memory cells of a Page of FLASH data. Referring to FIG. 1, the READ operation would involve the application of a first voltage level (such as a high voltage level) to the top portion of each bit line within the Block, the application of a second voltage level (such as a low voltage level or zero) to the bottom of each bit line within the Block, the application of a third voltage to the control gates of all of the memory cells within the Block that reside in Pages that are not being read, and the application of a fourth voltage to the control gates of all of the memory cells within the Block that reside in the Page that is being read. The voltage applied to the gates of the unread cells is sufficient in magnitude to render the corresponding transistors conductive, regardless of their programming state, yet smaller in magnitude than the voltage supplied to a control gate in order to program a cell. The voltage applied to the gates of the cells being read is such that their transistors will be rendered either conductive or non-conductive, depending upon their programming state. Since all unread cells within a bit line are rendered conductive, while the cells being read may be conductive or non-conductive, the voltage at the top of each bit line may be pulled low (conductive) or remain high (non-conductive). The voltage level at the top of a bit line, therefore, gives an indication of the status (programmed or unprogrammed) of the one cell being read within that bit line.
"For typical NAND flash memory devices in use at the time of this writing, the accumulated charge in a programmed cell will mandate a higher control gate voltage for the corresponding transistor to become conductive. Hence, a programmed cell will be non-conductive during a read operation and the top of the corresponding bit line will remain at a sufficiently high voltage to detect the fact that the cell being read has been programmed. Correspondingly, an unprogrammed cell will be conductive during a read operation and the top of the corresponding bit line will be pulled to a sufficiently low voltage to detect the fact that the cell being read has not been programmed. Taken as a whole, the voltage values at the top of the bit lines yield the programming status of all cells within a page being read.
"As the above shows, for the exemplary NAND FLASH memory devices, the performance of a READ operation on one or more storage cell tends to impose elevated voltage stresses on the other unread cells within the same Block. This stress arises from the application of an elevated voltage to the control gates of the unread cells, sufficient in magnitude to render the unread cells conductive, regardless of their programming states. Over time, repeated application of this higher magnitude voltage to the gates of a given cell in a FLASH memory can result in charge migrating onto the floating gate of the cell or into its charge-trapping region. Over time, this charge can accumulate to the point that the amount of charge on a cell that was previously reflective of a logic '0' (or low or no charge state) can rise to a level where the cell is weakly programmed and, when subject to a READ operation, will erroneously produce a reading reflecting the storage of a logic '1' (higher charge state). This weak programming resulting from the READ operation cannot always be predicted accurately and can result in a number of bits in memory cells not associated with the cells being read becoming corrupted such that one could no longer determine whether the originally stored data bit was a '1' or a '0.' Because the errors described above are induced by the disturbances created by the READ operation, they are known as 'Read Disturb' errors.
"While the preceding paragraphs describe operations and mechanisms generally encountered with SLC NAND FLASH memory, similar operations and mechanisms also pertain to MLC NAND FLASH memory. In such NAND FLASH memory devices, the control gates of unread cells are driven with a voltage that is guaranteed to render the unread cells conductive and that also leads to read disturbance in the unread cells. In such devices, the control gates of cells being read are driven with a different voltage, one that is such that the conductivity of the cell being read will differ based upon the quantity of charge stored in the cells' charge storage area or areas. MLC NAND FLASH memory is generally much more susceptible to read disturb errors than its SLC counterpart.
"Read Disturb errors are a recognized condition of NAND FLASH memories. The most common approach for addressing the issue of Read Disturb errors in NAND FLASH memories is to utilize one or more error correction and checking ('ECC') techniques. While there are a number of different ECC techniques, ECC generally involves the utilization of one or more code bits (in addition to the original stored data bits) to allow one to determine and, in some instances correct, errors that may occur in data associated with the specific ECC code bit(s). ECC is typically implemented on a Page level and typically with respect to Pages that include one or more storage elements and, therefore, store data items comprising multiple bits. Alternatively, the quantity of data associated with a group of ECC code bits may be a subset of the overall Page, allowing multiple data sets within the same Page to be checked and/or corrected independently of one another. If one of the data bits associated with a particular group of ECC code bits becomes corrupted, the ECC bits can be used to detect the corrupted bit and possibly reconstruct it.
"There are limitations associated with the use of ECC to address Read Disturb errors in NAND FLASH memory. For example, most ECC techniques are capable of identifying and addressing errors resulting from a disturbance of only one, or a small number of, the bits in the data item to which the ECC is applied. If more than one of the bits in the data item is disturbed, most ECC techniques will not be able to reconstruct the original data item. Moreover, if a large number of bits in a data item are errantly disturbed, certain ECC techniques will be incapable of identifying the existence of an error. Compounding this issue is the fact that Read Disturb errors occur in Pages that are not being read, while data and ECC bits must be read to perform checking and correction. Hence, the number of errors in a disturbed page can grow from a correctable number to an uncorrectable number without any warning that the seriousness of the induced errors is increasing. Thus, while ECC techniques may be widely utilized, they are not always effective.
"Another approach used to address Read Disturb errors in NAND FLASH memory devices is to maintain a count of the number of times a given Block is accessed after an ERASE operation has occurred and to move the data in the Block to a new location and then perform an ERASE operation on the original Block if the READ count for the Block exceeds a pre-established number. While this approach can potentially avoid certain Read Disturb errors, it can limit the performance of a device or system utilizing this technique since the movement of the Block of data imposes burdens on the device or system in terms of overhead, speed, efficiency, power and other aspects that can degrade the overall performance of the device or system. Not only does it take an appreciable amount of overhead in terms of processing power and time to move the entire Block of data, the ERASE operation for the original Block can be time consuming. For systems where high speed read operations are desired, such burdens are undesirable and inefficient.
"Another issue associated with the approach of maintaining a count and moving and erasing a data Block when the READ count for the Block is exceeded is that it imposes upon the system a relatively large number of ERASE operations. In particular, because the entire contents of a Block are moved and erased each time the predetermined count for that Block is exceeded, the processing of the data in a given Block that includes multiple, frequently accessed Pages, will require a large number of ERASE operations over the lifetime of the product. Because FLASH memory devices do not have unlimited lifetimes and because a given FLASH memory cell is subject to failure upon the occurrence of a given number of ERASE operations that will vary from manufacturer to manufacturer and from device to device, the described system tends to shorten the overall useful life of the devices within a FLASH memory system.
"Accordingly, what is needed is a more effective and efficient way to reduce Read Disturb errors in NAND FLASH memories."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "The disclosed embodiments are directed to methods and apparatuses for providing efficient detection and reduction of Read Disturb errors in NAND FLASH memory. In some embodiments, the methods and apparatuses involve a plurality of FLASH memory devices in a NAND FLASH memory system, and a system controller configured to organize the FLASH memory devices into a plurality of blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. Each FLASH memory device comprises a plurality of FLASH memory cells configured to store data received from a source external to the FLASH memory device. At least one of the FLASH memory devices further comprises at least one modified memory cell associated with the plurality of FLASH memory cells that is configured differently from the other cells (for example in terms of its construction, the voltages applied to the cell, or the manner in which it is utilized) so that this modified cell is more susceptible to a read disturb error than the other cells within the plurality of FLASH memory cells.
"In some embodiments, methods and apparatuses involve an apparatus for inhibiting and/or mitigating the severity of errors in a group of memory cells in a FLASH memory device. Such an apparatus may comprise at least one detecting cell having a floating gate transistor that is associated with the group of memory cells, and circuitry for applying a voltage to a gate of the detecting cell each time one of the memory cells within the group of memory cells is accessed as part of a READ operation. The apparatus may further comprise a sensor coupled to the detecting cell and adapted to sense a voltage or other electrical signal associated with the detecting cell that corresponds to the amount of charge stored on the floating gate of the transistor of the detecting cell. A comparator may also be coupled to the sensor and adapted to compare the sensed voltage or other electrical signal to a reference voltage or other reference electrical signal and provide an output, the output of the comparator generally providing an indication of increased likelihood of an error occurring within the group of memory cells.
"In some embodiments, the methods and apparatuses involve a flash memory device comprising a FLASH memory space formed from a plurality of memory cells. The FLASH memory space contains physical address locations to which data may be stored, the physical address locations being grouped into Pages and at least one Block, where each Page comprises a plurality of physical address locations that are addressed at the same time and each Block comprises a collection of physical address locations that may be erased through a single erase operation. The flash memory device also comprises a detecting mechanism associated with at least one Block for providing an output signal (possibly a voltage) indicative of potential errors among the memory cells within the Block. The flash memory device further comprises means for receiving a READ request directed to a given Page within the Block and for providing a voltage to: (i) the memory cells in the Pages within the Block that are not the target of the READ request, and (ii) the detecting mechanism."
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Keywords for this news article include: Electronics, High Voltage,
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