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Patent Issued for Nonvolatile Memory Cell Operating by Increasing Order in Polycrystalline Semiconductor Material

June 4, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- SanDisk 3D LLC (Milpitas, CA) has been issued patent number 8730720, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Herner, Scott Brad (San Jose, CA); Bandyopadhyay, Abhijit (San Jose, CA).

This patent was filed on June 25, 2013 and was published online on May 20, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "The invention relates to a nonvolatile one-time-programmable memory cell.

"Prior art nonvolatile memories, such as Johnson et al. U.S. Pat. No. 6,034,882, 'Vertically Stacked Field Programmable Nonvolatile Memory and Method of Fabrication,' have been based on a memory cell pairing a semiconductor junction diode with a dielectric antifuse layer, the diode and the dielectric antifuse layer disposed between conductors.

"When the memory cell is formed, the dielectric antifuse layer (typically a layer of silicon dioxide) acts as an insulator, and when a read voltage is applied between the conductors, very little current flows between the conductors. When a sufficiently large voltage is applied between the conductors, however, the dielectric antifuse layer suffers dielectric breakdown and ruptures, and a permanent conductive path is formed through the dielectric antifuse layer.

"In a programmed cell, when a read voltage is applied between conductors, a significantly higher current flows than in the unprogrammed cell, allowing the unprogrammed and programmed cells to be distinguished. The memory state is stored in the state of the dielectric antifuse layer, which may be intact or ruptured.

"Memory cells based on rupture of a dielectric antifuse layer, however, suffer some disadvantages. If the dielectric antifuse layer is too thin, leakage current can be a severe problem. Disturb can also be a problem: every time the memory cell is read, the dielectric antifuse layer is exposed to some stress, and may eventually break down and be inadvertently programmed. This is avoided by making the dielectric antifuse layer thicker, but a thicker dielectric antifuse layer requires higher programming voltage to rupture.

"Higher voltages in electronic devices, for example in portable devices, are generally disadvantageous. If the dielectric antifuse layer is an oxide layer formed by oxidation, a thicker antifuse layer calls for either higher temperatures or slower fabrication time, both disadvantageous in forming a commercial device.

"There is a need, therefore, for a one-time programmable memory cell which does not rely on rupture of a dielectric antifuse layer."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "The present invention is defined by the following claims, and nothing in this section should be taken as a limitation on those claims. In general, the invention is directed to a nonvolatile memory cell comprising a diode, the memory state stored in the state of the diode.

"A first aspect of the invention provides for a nonvolatile memory cell including: a first conductor; a diode comprising amorphous or polycrystalline semiconductor material; and a second conductor, the semiconductor diode disposed between the first conductor and the second conductor, wherein before application of a programming voltage the diode has a first maximum barrier height, and after application of the programming voltage the diode has a second maximum barrier height, the second maximum barrier height at least 1.5 times the first maximum barrier height.

"Another aspect of the invention provides for a nonvolatile memory cell including: a first conductor; a second conductor; and a polycrystalline semiconductor junction diode disposed between the first and second conductors, wherein a data state of the memory cell is determined by a state of an antifuse, and wherein the polycrystalline semiconductor junction diode is the antifuse.

"Yet another aspect of the invention provides for a method for forming and programming a nonvolatile memory cell, the method including: forming a first conductor; forming a second conductor; depositing and doping semiconductor material to form a semiconductor junction diode, the semiconductor junction diode disposed between the first and second conductors; crystallizing the semiconductor material such that the semiconductor junction diode is polycrystalline, wherein, during the crystallizing step, the semiconductor material is not in contact with a template material having a lattice mismatch of less than 12 percent with the semiconductor material; and programming the memory cell by applying a programming voltage between the first and second conductors, wherein no resistance-switching element having its resistance changed by application of the programming voltage by more than a factor of two is disposed between the semiconductor junction diode and the first conductor or between the semiconductor junction diode and the second conductor.

"A preferred embodiment of the invention provides for a monolithic three dimensional memory array including: a) a first memory level above a substrate, the first memory level comprising: i) a first plurality of substantially parallel conductors; ii) a second plurality of substantially parallel conductors above the first conductors; iii) a first plurality of semiconductor junction diodes, each first diode disposed between one of the first conductors and one of the second conductors; and iv) a first plurality of one-time-programmable memory cells, each first memory cell adapted to be programmed by application of a programming voltage, each memory cell comprising a portion of one of the first conductors, a portion of one of the second conductors, and one of the first diodes, wherein before programming, each first diode has a first maximum barrier height, and after programming, each first diode has a second maximum barrier height, the second maximum barrier height at least 1.5 times the first maximum barrier height; and b) a second memory level monolithically formed above the first memory level.

"Another preferred embodiment of the invention provides for a monolithic three dimensional memory array including: a) a first memory level comprising: i) a plurality of bottom conductors; ii) a plurality of top conductors; and iii) a plurality of first polycrystalline semiconductor junction diodes, each diode disposed between one of the bottom and one of the top conductors; and iv) a first memory cell comprising one of the first diodes, wherein the data state of the first memory cells is determined by the state of an antifuse, and wherein the diode of the first memory cell is the antifuse; and b) a second memory level monolithically formed above the first memory level.

"A final aspect of the invention provides for a nonvolatile memory cell including: a first conductor; a diode comprising amorphous or polycrystalline semiconductor material; and a second conductor, the semiconductor diode disposed between the first conductor and the second conductor, wherein before application of a programming voltage the diode has a first rectification ratio at a read voltage between about 0.5 and about 2.5 volts, and after application of the programming voltage the diode has a second rectification ratio at the read voltage, the second rectification ratio at least 10 times the first rectification ratio.

"Each of the aspects and embodiments of the invention described herein can be used alone or in combination with one another.

"The preferred aspects and embodiments will now be described with reference to the attached drawings."

For the URL and additional information on this patent, see: Herner, Scott Brad; Bandyopadhyay, Abhijit. Nonvolatile Memory Cell Operating by Increasing Order in Polycrystalline Semiconductor Material. U.S. Patent Number 8730720, filed June 25, 2013, and published online on May 20, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=56&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=2767&f=G&l=50&co1=AND&d=PTXT&s1=20140520.PD.&OS=ISD/20140520&RS=ISD/20140520

Keywords for this news article include: Electronics, Semiconductor, SanDisk 3D LLC.

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Source: Electronics Newsweekly


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