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Patent Issued for Method for Making FINFETs and Semiconductor Structures Formed Therefrom

June 4, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Zhu, Huilong (Poughkeepsie, NY); Luo, Zhijiong (Poughkeepsie, NY); Yin, Haizhou (Poughkeepsie, NY), filed on November 30, 2011, was published online on May 20, 2014.

The assignee for this patent, patent number 8729638, is Institute of Microelectronics, Chinese Academy of Sciences (Beijing, P.R., CN).

Reporters obtained the following quote from the background information supplied by the inventors: "As the semiconductor industry advances to the 22 nm technology node, some manufacturers have already begun to consider the problem of how to make transition from a planar CMOS transistor to a three-dimensional (3D) FinFET device structure. Compared to a planar transistor, a FinFET device improves control over the channel, and thus reduces short-channel effect. The gate of a planar transistor is located right over the channel, while the gate of a FinFET device surrounds the channel from two or three sides, thus electrostatic control may be implemented for the channel from two or three sides.

"At present, normally there are two types of conventional FinFETs: FinFETs formed on a substrate of a Silicon-On-Insulator (SOI), and FinFETs formed on a substrate of a bulk Si material (Bulk FinFETs). However, using of SOI wafers to make FinFETs is very expensive. In another aspect, it is difficult to make high-quality FinFETs with conventional bulk wafers due to the problems in terms of device width and sub-threshold leakage control."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "The structure and method disclosed by the invention relate to making a FinFET with conventional wafer. The FinFET of the invention has as good performance in control of device width and sub-threshold leakage as the FinFET made by use of a SOI.

"In order to realize the objective, according to an aspect of the invention, a method for making a Fin Field-Effect Transistor is provided, comprising: providing a semiconductor substrate, a SiGe layer on the semiconductor substrate and a Si layer on the SiGe layer, wherein the lattice constant of the SiGe layer matches with that of the substrate; patterning the Si layer and the SiGe layer to form a Fin structure; forming a gate stack on top and both sides of the Fin structure and a spacer surrounding the gate stack; removing a portion of the Si layer which is outside the spacer with the spacer as a mask, while keeping a portion of the Si layer which is inside the spacer; removing a portion of the SiGe layer which is kept after the patterning, to form a void; forming an insulator in the void; and epitaxially growing stressed source and drain regions located on both sides of the Fin structure and the insulator.

"According to another aspect of the invention, a semiconductor structure is provided, comprising: a semiconductor substrate; an insulator formed on the semiconductor substrate; a Fin structure formed over the insulator; a gate stack and a spacer surrounding the gate stack, which are formed over the Fin structure; and source and drain regions located on both sides of the Fin structure and the insulator, wherein, the source and drain regions are formed of a stressed material for enhancing the carrier mobility of the channel.

"Besides the advantages mentioned above, the invention further has advantageous effect as follows:

"the FinFET may be formed by a bulk semiconductor substrate, such that the device width can be easily adjusted; the insulator increases the distance between the gate and the source/drain, such that the parasitic capacitance may be reduced; the area of the source/drain increases, such that the source/drain resistance may be reduced; spacing regions are formed between the source and drain, such that the SCE (Short Channel Effect) may be reduced; the stressed source/drain may enhance the strain of a channel."

For more information, see this patent: Zhu, Huilong; Luo, Zhijiong; Yin, Haizhou. Method for Making FINFETs and Semiconductor Structures Formed Therefrom. U.S. Patent Number 8729638, filed November 30, 2011, and published online on May 20, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=77&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=3844&f=G&l=50&co1=AND&d=PTXT&s1=20140520.PD.&OS=ISD/20140520&RS=ISD/20140520

Keywords for this news article include: Semiconductor, Institute of Microelectronics Chinese Academy of Sciences.

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Source: Electronics Newsweekly


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