This patent application is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "This invention is related to the field of integrated circuit design, and more particularly, to detecting jitter on an integrated circuit.
"Digital logic designs generally include asynchronous logic blocks separated by clocked storage circuits. At the beginning of a clock cycle, the clock storage circuits launch previously stored logic signals into an asynchronous logic block. The logic signals then propagate through the asynchronous logic block and are operated on in accordance with the logic function implemented in the asynchronous logic block. At the end of the clock cycle, the resultant logic signals are captured by another set of clocked storage elements.
"In real integrated circuits, however, clock signals are not ideal. The period of a clock signal may vary from one cycle to another. This variation in a clock signal is commonly referred to as 'jitter,' and may have numerous sources such as, variations in the clock generator (phase-locked loop), variation in power supply voltages, capacitive or inductive coupling into the clock signal from other nearby signals, and the like.
"When designing digital logic circuits, digital logic designs allow for a certain amount of jitter (commonly referred to as 'adding margin') which limits the effect portion of a clock cycle in which logic work may be done. In some cases the added margin is estimated based on an analysis of the clock generation circuits, such as, e.g., phase-locked loops, characteristics of the semiconductor manufacturing process that will be used to fabricate the design, the clock distribution network, etc. After fabrication, the actual circuit may experience less jitter than estimated which would allow for a higher operation frequency. Alternatively, the actual circuit may be experience more jitter than estimated, which may prevent the circuit from achieving intended performance goals."
In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "Various embodiments of circuit for determining the jitter of integrated circuit are disclosed. Broadly speaking, a circuit and a method are contemplated in which, a launch clock phase may be selected. A data signal may be generated by a data generator signal in response to the launch clock. The data signal may then be delayed to generate a plurality of delayed data signals. Each of the delayed data signals may then be captured by a plurality of clocked storage elements. A detector circuit may then compare the outputs of the plurality of clocked storage elements to determine which of the delayed data signals were captured in error. A storage circuit may accumulate an indication of which of the delayed data signals were captured in error.
"In another embodiment, the frequency of the data signal may be half of the frequency of the launch clock. The accumulation of the indication of delay data signals were captured in error may be reset in response to a reset signal.
"In a further embodiment, the delay generator signal may provide two delay offsets to the delay signal. The determination of which delay offset to provide may be dependent upon the phase of the launch clock.
BRIEF DESCRIPTION OF THE DRAWINGS
"The following detailed description makes reference to the accompanying drawings, which are now briefly described.
"FIG. 1 illustrates an embodiment of a system on a chip.
"FIG. 2 illustrates an embodiment of a clock distribution network.
"FIG. 3 illustrates an example clock waveform.
"FIG. 4 illustrates block diagram of an integrated circuit including one or more jitter detectors.
"FIG. 5 illustrates an embodiment of a jitter detector.
"FIG. 6 illustrates an embodiment of a clock phase selection circuit.
"FIG. 7 illustrates an embodiment of a data generator circuit.
"FIG. 8 illustrates an embodiment of a captured data comparison circuit.
"FIG. 9 illustrates a flowchart depicting a method of determining jitter for a clock cycle.
"FIG. 10 illustrates a flowchart depicting a method of accumulating jitter data over multiple clock cycles.
"While the disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the disclosure to the particular form illustrated, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims. The headings used herein are for organizational purposes only and are not meant to be used to limit the scope of the description. As used throughout this application, the word 'may' is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words 'include,' 'including,' and 'includes' mean including, but not limited to.
"Various units, circuits, or other components may be described as 'configured to' perform a task or tasks. In such contexts, 'configured to' is a broad recitation of structure generally meaning 'having circuitry that' performs the task or tasks during operation. As such, the unit/circuit/component can be configured to perform the task even when the unit/circuit/component is not currently on. In general, the circuitry that forms the structure corresponding to 'configured to' may include hardware circuits. Similarly, various units/circuits/components may be described as performing a task or tasks, for convenience in the description. Such descriptions should be interpreted as including the phrase 'configured to.' Reciting a unit/circuit/component that is configured to perform one or more tasks is expressly intended not to invoke 35 U.S.C. .sctn.112, paragraph six interpretation for that unit/circuit/component. More generally, the recitation of any element is expressly intended not to invoke 35 U.S.C. .sctn.112, paragraph six interpretation for that element unless the language 'means for' or 'step for' is specifically recited."
URL and more information on this patent application, see: Hess, Greg M; Burnette, II, James E. Selectable Phase Or Cycle Jitter Detector. Filed
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