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Researchers Submit Patent Application, "Semiconductor Memory Device and Method of Operating the Same", for Approval

May 29, 2014



By a News Reporter-Staff News Editor at Politics & Government Week -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventor JEON, Yoo Nam (Gyeonggi-do, KR), filed on March 16, 2013, was made available online on May 15, 2014.

The patent's assignee is Sk Hynix Inc.

News editors obtained the following quote from the background information supplied by the inventors: "Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor memory device and a method of operating the same.

"Semiconductor memory devices are classified into volatile memory devices and non-volatile memory devices.

"A volatile memory device may perform a read/write operation at a high speed, but may lose data stored therein in a non-powered condition. Meanwhile, a non-volatile memory device performs at relatively slow speed in the read/write operation, but may maintain the stored data even when a power is blocked. Accordingly, the non-volatile memory device is used for storing data, which is to be maintained irrespective of being supplied with the power or not. The non-volatile memory devices include a read-only memory (ROM), a mask read-only memory (MROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a phase-change random access memory (PRAM), a magnetic random access memory (MRAM), a resistive random access memory (RRAM), a ferroelectric random access memory (FRAM), and a flash memory. The flash memories are classified into a NOR-type flash memory and a NAND-type flash memory.

"The flash memories have an advantage of a random access memory (RAM) for freely programming and erasing data and an advantage of a read-only memory (ROM) for maintaining the stored data even in a non-powered condition. The flash memories have been widely used as a storage medium of portable electronic devices, such as a digital camera, a personal digital assistant PDA, and an MP3 player.

"Recently, size of memory cells in the flash memory has reduced and space between the memory cells became narrower. Therefore, threshold voltage distribution of the memory cells may be deteriorated due to interferences between the adjacent memory cells."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventor's summary information for this patent application: "Exemplary embodiments of the present invention are directed to a semiconductor memory device that may improve threshold voltage distribution of memory cells and a method of operating the same.

"A method of operating a semiconductor memory device in accordance with one embodiment of the present invention may include increasing threshold voltage of memory cells by performing an LSB program operation on the memory cells having first state, decreasing threshold voltage of memory cells to be programmed to second state of the memory cells to a level lower than a first level in unit of a memory cell for an MSB program operation, and increasing threshold voltage of memory cells to be programmed to third state of the memory cells to a level higher than a second level, which is higher than the first level, in unit of a memory cell for the MSB program operation.

"A semiconductor memory device in accordance with one embodiment of the present invention may include a memory cell array configured to include memory cells, an operation circuit configured to perform an LSB program operation and an MSB program operation on memory cells having first state, and a control circuit configured to control the operation circuit, to decrease threshold voltage of a memory cell to be programmed to second state to a level lower than a first level, to increase threshold voltage of a memory cell to be programmed to third state to a level more than a second level, and to increase threshold voltage of a memory cell to be programmed to fourth state to a level more than a third level when an MSB program operation is performed. Here, the second level is higher than the first level, and the third level is higher than the second level.

"A semiconductor memory device in accordance with another embodiment of the present invention may include a memory cell array configured to include memory cells, an operation circuit configured to increase or decrease threshold voltage of the memory cells, and a control circuit configured to control the operation circuit, to increase threshold voltage of a memory cell, where first data is to be stored, in a first page for programming of multi bit data to a level more than a first level, and to decrease threshold voltage of a memory cell, where second data is to be stored, to a level lower than second level that is lower than the first level.

"In accordance with the embodiments of the present invention, threshold voltage distribution of memory cells in a semiconductor memory may be improved by reducing change of threshold voltage of the memory cells due to interferences between the memory cells.

BRIEF DESCRIPTION OF THE DRAWINGS

"The above and other features and advantages of the present invention will become readily apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:

"FIG. 1 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention;

"FIG. 2 is a detailed diagram illustrating a memory block shown in FIG. 1;

"FIG. 3 is a detailed diagram illustrating a page buffer shown in FIG. 1;

"FIG. 4 is a view for explaining first program process;

"FIG. 5 is a view for explaining second program process;

"FIG. 6 is a view for explaining third program process in accordance with an embodiment of the present invention;

"FIG. 7 is a flowchart illustrating a method of operating a semiconductor memory device using the third program process in accordance with the embodiment of the present invention;

"FIG. 8 is a view for explaining program order in accordance with the embodiment of the present invention;

"FIG. 9 is a view for explaining an erase operation in accordance with the embodiment of the present invention;

"FIG. 10 is a table for explaining voltage supply condition in a program operation and a erase operation in accordance with the embodiment of the present invention;

"FIG. 11 is a block diagram illustrating a memory system including a non-volatile memory device for performing an operation in accordance with the embodiment of the present invention;

"FIG. 12 is a block diagram illustrating a fusion memory device or a fusion memory system for performing an operation in accordance with the embodiment of the present invention; and

"FIG. 13 is a view illustrating a computing system including a flash memory device for performing an operation in accordance with the embodiment of the present invention."

For additional information on this patent application, see: JEON, Yoo Nam. Semiconductor Memory Device and Method of Operating the Same. Filed March 16, 2013 and posted May 15, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=3925&p=79&f=G&l=50&d=PG01&S1=20140508.PD.&OS=PD/20140508&RS=PD/20140508

Keywords for this news article include: Electronics, Sk Hynix Inc, Semiconductor, Random Access Memory.

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Source: Politics & Government Week


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