News Column

Patent Issued for Hot-Plugging Debugger Architectures

May 27, 2014



By a News Reporter-Staff News Editor at Journal of Technology -- A patent by the inventors Garnier, Sylvain (Nantes, FR); Rouaux, Anthony (Mauves sur Loire, FR); Jouin, Sebastien (La Chapelle-Launay, FR); Pedersen, Frode Milch (Trondheim, NO), filed on September 21, 2012, was published online on May 13, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8726223 is assigned to Atmel Corporation (San Jose, CA).

The following quote was obtained by the news editors from the background information supplied by the inventors: "Device developers may use hardware debuggers to debug a device. A hardware debugger can use a Joint Test Action Group (JTAG) based interface to gain control of a processor. A debugging application, running on a host device, can connect with the hardware debugger to perform operations such as setting software breakpoints, monitoring processor states, reading data, or writing data to one or more locations such as a processor register."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "This document describes, among other things, technologies relating to hot-plugging debugger architectures. In one aspect, a described processor-chip, e.g., integrated circuit device, includes a processor, a first pad interface, a detector configured to detect a clock signal via the first pad interface, one or more second pad interfaces, two or more components including a debug system that is communicatively coupled with the processor, a multiplexer communicatively coupled with the one or more second pad interfaces and the two or more components, and configured to selectively interconnect the one or more second pad interfaces with a selected component of the two or more components. The multiplexer can be configured to cause the debug system to be the selected component when the clock signal is detected via the first pad interface.

"This and other implementations can include one or more of the following features. Implementations can include circuitry to detect an override event associated with a reassignment of the first pad interface. The override event can cause the detector to suspend detection of the clock signal on the first pad interface such that the first pad interface becomes usable as a general purpose input interface, output interface, or both. The one or more second pad interfaces can include two or more pad interfaces. The two or more components includes a general purpose input/output (GPIO) controller that is communicatively coupled with the processor. Implementations can include circuitry configured to generate an override signal to prevent further detection of a debug probe on the first pad interface. Implementations can include circuitry configured to generate an override signal to change an assignment of the first pad interface from the debug system to the GPIO controller; and circuitry configured to register the override signal to maintain the assignment to the GPIO controller. Implementations can include circuitry configured to determine a protection status of a non-volatile memory that is communicatively coupled with the processor; and circuitry configured to cause a generation of the selection signal when the protection status indicates an unprotected state. In some implementations, the first pad interface is connectable with a debug clock signal interface of a debug probe that provides the clock signal, the debug system being responsive to a connection of the debug probe that occurs after the processor-chip has transitioned to an active state.

"A hot-plugging debugger system can include a processor, a first pad interface, a detector configured to detect a clock signal via the first pad interface, one or more second pad interfaces, a debug system communicatively coupled with the processor, a GPIO controller communicatively coupled with the processor, a multiplexer communicatively coupled with the one or more second pad interfaces and a group of resources including the debug system and the GPIO controller, the multiplexer being configured to selectively interconnect the one or more second pad interfaces with a selected resource of the group of resources based on a selection signal, and a selector configured to produce the selection signal such that the multiplexer interconnects the one or more second pad interfaces with the debug system when the clock signal is detected via the first pad interface.

"A hot-plugging debugger technique can include causing a processor-chip to start-up and transition to an active state without a debug probe attached to a first pad interface of the processor-chip; operating a multiplexer of the processor-chip to selectively interconnect one or more second pad interfaces with two or more components of the processor-chip, the components including a debug system; detecting, when the processor-chip is in the active state, an attachment of the debug probe to the first pad interface by observing a clock signal from the debug probe via the first pad interface; and generating, in response to the attachment, a selection signal that causes the multiplexer to interconnect the one or more second pad interfaces with the debug system.

"Particular embodiments of the technology described in this document can be implemented so as to realize one or more of the following advantages. A hot-plugging debugger architecture can allow the activation of a chip-level debug interface after a processor chip is already executing applications and/or firmware. With such an architecture, a debug probe can be attached to a processor chip at any time, including after the chip has been brought-up. One or more described technologies can multiplex pins on the processor chip between debugging and non-debugging proposes. Multiplexing pins on a processor chip can reduce the total number of pins required by the processor chip. One or more described technologies can selectively enable a hot-plugging debugger capability based on a memory protection status, which can provide debugging flexibility to device manufactures during development and/or assembly-line testing and then can be turned-off when shipped to prevent or limit access to a device's firmware.

"The details of one or more embodiments of the subject matter described in this document are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims."

URL and more information on this patent, see: Garnier, Sylvain; Rouaux, Anthony; Jouin, Sebastien; Pedersen, Frode Milch. Hot-Plugging Debugger Architectures. U.S. Patent Number 8726223, filed September 21, 2012, and published online on May 13, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=15&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=729&f=G&l=50&co1=AND&d=PTXT&s1=20140513.PD.&OS=ISD/20140513&RS=ISD/20140513

Keywords for this news article include: Technology, Atmel Corporation.

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Source: Journal of Technology


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