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Patent Issued for Heterojunction Compound Semiconductor Protection Clamps and Methods of Forming the Same

May 28, 2014



By a News Reporter-Staff News Editor at Journal of Engineering -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Parthasarathy, Srivatsan (Acton, MA); Salcedo, Javier Alejandro (North Billerica, MA); Zhang, Shuyun (Allston, MA), filed on September 24, 2012, was published online on May 13, 2014.

The patent's assignee for patent number 8723227 is Analog Devices, Inc. (Norwood, MA).

News editors obtained the following quote from the background information supplied by the inventors: "Embodiments of the invention relate to electronic systems, and more particularly, to protection devices for compound semiconductor circuitry, such as gallium arsenide (GaAs) circuitry.

"Electronic circuits can be exposed to a transient electrical event, or an electrical signal of a relatively short duration having rapidly changing voltage and high power. Transient electrical events can include, for example, electrical discharge/electrostatic overstress (ESD/EOS) events arising from the abrupt release of charge from an object or person to an electronic circuit. Transient electrical events can damage an integrated circuit (IC) due to overvoltage conditions and/or high levels of power dissipation over relatively small areas of the IC. High power dissipation can increase circuit temperature, and can lead to numerous problems, such as junction damage, metal damage, and/or surface charge accumulation.

"Transient electrical event protection can be difficult to provide for certain gallium arsenide (GaAs) or other compound semiconductor circuitry, including, for example, radio frequency (RF) power amplifiers, attenuators, gain blocks, multi-voltage circuits, drivers, and/or switches. For instance, conventional ESD/EOS protection devices can have a large parasitic capacitance that can adversely impact circuit gain, linearity, and/or bandwidth, and thus can be unsuitable for protecting such circuits. Additionally, the performance of ESD/EOS protection devices can be limited by the relatively low thermal conductivity and/or current-handling capability associated with compound semiconductor technologies. Accordingly, there is a need for improved devices and circuits for providing protection to compound semiconductor circuitry."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "In one embodiment, an apparatus includes a multi-gate high electron mobility transistor (HEMT) including a drain/source, a source/drain, a first depletion-mode (D-mode) gate, a second D-mode gate, and an enhancement-mode (E-mode) gate. The E-mode gate is disposed between the first and second D-mode gates. The drain/source and the first D-mode gate are electrically connected to a first terminal, and the source/drain and the second D-mode gate are electrically connected to a second terminal. The current limiting circuit is electrically connected between the E-mode gate and the second terminal. The apparatus further includes a forward trigger control circuit electrically connected between the first terminal and the E-mode gate, and the forward trigger control circuit is configured to conduct a trigger current when a voltage of the first terminal exceeds a voltage of the second terminal by a forward trigger voltage. The trigger current is configured to turn-on the E-mode gate to provide a forward conduction path between the first terminal and the second terminal.

"In another embodiment, an apparatus includes a substrate, a heterojunction structure disposed over the substrate, a drain/source region disposed over the heterojunction structure and electrically connected to a first terminal, a source/drain region disposed over the heterojunction structure and electrically connected to a second terminal, an E-mode gate region disposed over the heterojunction structure between the drain/source region and the source/drain region, a first D-mode gate region disposed over the heterojunction structure between the drain/source region and the E-mode gate region, a second D-mode gate region disposed over the heterojunction structure between the source/drain region and the E-mode gate region, a current limiting circuit electrically connected between the E-mode gate region and the second terminal, and a forward trigger control circuit electrically connected between the first terminal and the E-mode gate region. The first D-mode gate region is electrically connected to the first terminal, and the second D-mode gate region is electrically connected to the second terminal.

"In another embodiment, a method of making a protection clamp is provided. The method includes forming a heterojunction structure over a substrate, forming a drain/source region over the heterojunction structure, forming a source/drain region over the heterojunction structure, forming an E-mode gate region over the heterojunction structure, forming a first D-mode gate region over the heterojunction structure, forming a second D-mode gate region disposed over the heterojunction structure, forming a current limiting circuit, and forming a forward trigger control circuit. The E-mode gate region is disposed between the drain/source region and the source/drain region, and the first D-mode gate region is disposed between the drain/source region and the E-mode gate region. Additionally, the second D-mode gate region is disposed between the source/drain region and the E-mode gate region. The current limiting circuit includes a first terminal electrically connected to the E-mode gate region and a second terminal electrically connected to the second D-mode gate region and to the source/drain region. The forward trigger control circuit includes a first terminal electrically connected to the E-mode gate region and a second terminal electrically connected to the first D-mode gate region and to the drain/source region."

For additional information on this patent, see: Parthasarathy, Srivatsan; Salcedo, Javier Alejandro; Zhang, Shuyun. Heterojunction Compound Semiconductor Protection Clamps and Methods of Forming the Same. U.S. Patent Number 8723227, filed September 24, 2012, and published online on May 13, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=75&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=3709&f=G&l=50&co1=AND&d=PTXT&s1=20140513.PD.&OS=ISD/20140513&RS=ISD/20140513

Keywords for this news article include: Chemicals, Chemistry, Electronics, Semiconductor, Gallium Arsenide, Analog Devices Inc., Medical Device Companies.

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Source: Journal of Engineering


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