The assignee for this patent application is
Reporters obtained the following quote from the background information supplied by the inventors: "As those skilled in the pertinent art are aware, applications may be executed in parallel to increase their performance. Data parallel applications carry out the same process concurrently on different data. Task parallel applications carry out different processes concurrently on the same data. Static parallel applications are applications having a degree of parallelism that can be determined before they execute. In contrast, the parallelism achievable by dynamic parallel applications can only be determined as they are executing. Whether the application is data or task parallel, or static or dynamic parallel, it may be executed in a pipeline which is often the case for graphics applications.
"Certain computing systems, such as a single-instruction, multiple-data (SIMD) processor, are particularly adept at executing data parallel applications. A pipeline control unit in the SIMD processor creates groups of threads of execution and schedules them for execution, during which all threads in the group execute the same instruction concurrently. In one particular processor, each group has 32 threads, corresponding to 32 execution pipelines, or lanes, in the SIMD processor.
"Consider a fork-join parallel programming model such as OpenMP or OpenACC implemented on a parallel processing computing system. In this model, some parts of a program's code are executed by only one thread (a 'master' thread) while other parts are executed by multiple threads in parallel ('worker' threads). Execution starts with only the master thread active. At a work creation construct, execution is forked when the master thread activates worker threads and assigns each worker an 'execution task,' such as a certain number of iterations of a loop. Worker threads then typically execute their assigned tasks in parallel. Once the worker threads are finished, they deactivate, and execution is joined when the master thread resumes execution of the remainder of the program code. The period of program execution when only one thread is active will be referred to herein as the sequential region or phase, and the period of program execution when more than one thread is active will be referred to herein as the parallel region or phase.
"In many fork-join models, including OpenMP and OpenACC, data objects allocated in the sequential region can be accessed in the parallel region. Accordingly, parallel processor architectures provide memory for storing the data objects to which multiple threads may gain access during their execution. This memory may be characterized by many properties, including size, latency, volatility and others and their accompanying advantages and disadvantages."
In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "One aspect provides a system for allocating shared memory of differing properties to shared data objects and a hybrid stack data structure. In one embodiment, the system includes: (1) a hybrid stack creator configured to create, in the shared memory, a hybrid stack data structure having a lower portion having a more favorable property and a higher portion having a less favorable property and (2) a data object allocator associated with the hybrid stack creator and configured to allocate storage for shared data object in the lower portion if the lower portion has a sufficient remaining capacity to contain the shared data object and alternatively allocate storage for the shared data object in the higher portion if the lower portion has an insufficient remaining capacity to contain the shared data object.
"Another aspect provides a method of allocating shared memory of differing properties to shared data objects. In one embodiment, the method includes: (1) creating a hybrid stack data structure in the shared memory, the data structure having a lower portion having a more favorable property and a higher portion having a less favorable property, (2) when a thread requires a shared data object, (2a) allocating storage for the shared data object in the lower portion if the lower portion has a sufficient remaining capacity to contain the shared data object and (2b) alternatively allocating storage for the shared data object in the higher portion if the lower portion has an insufficient remaining capacity to contain the shared data object and (3) when no thread further requires the shared data object, deallocating the storage.
"Yet another aspect provides a hybrid stack data structure. In one embodiment, the data structure includes: (1) a lower portion in a shared memory having a more favorable property and (2) a higher portion in the shared memory having a less favorable property.
"Reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
"FIG. 1 is a block diagram of a parallel processor operable to contain or carry out a system or method for allocating memory of differing properties to shared data objects;
"FIG. 2 is a diagram of one embodiment of a hybrid stack;
"FIG. 3 is a block diagram of one embodiment of a system for allocating memory of differing latency to shared data objects; and
"FIG. 4 is a flow diagram of one embodiment of a method of allocating memory of differing properties to shared data objects."
For more information, see this patent application: Marathe, Jaydeep; Chakrabarti,
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