No assignee for this patent application has been made.
Reporters obtained the following quote from the background information supplied by the inventors: "The present invention relates in general to data processing, and in particular, to input/output (I/O) in a data processing system.
"A data processing system may include multiple processing elements and multiple input/output adapters (IOAs) to support connections to communication networks, storage devices and/or storage networks, and peripheral devices. In such data processing systems, the hardware resources of the data processing system may be logically partitioned into multiple, non-intersecting sets of resources, each controlled by a respective one of multiple possibly heterogeneous operating system instances. The operating systems concurrently execute on this common hardware platform in their respective logical partitions (LPARs) under the control of system firmware, which is referred to as a virtual machine monitor (VMM) or hypervisor. Thus, the hypervisor allocates each LPAR a non-intersecting subset of the resources of the data processing system, and each operating system instance in turn directly controls its distinct set of allocable resources, such as regions of system memory and IOAs.
"In general, the IOAs in a data processing system employ an I/O address space that is distinct from the physical (real) address space utilized to address system memory in the data processing system. Consequently, address translation tables, referred to in the art as translation control entry (TCE) tables, are employed to translate addresses between the I/O address space and the real address space of the data processing system."
In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "Translation control entry (TCE) tables conventionally employ either a monolithic (i.e., a single-level) structure, or alternatively, a multi-level structure having a predetermined number of levels. Monolithic TCE tables can provide improved performance because only a single memory access is required to obtain any translation between the I/O address space and the real address space. Multi-level TCE tables, on the other hand, are generally easier to manage because the storage locations for the additional translations required as the data processing system continues to run need not be contiguous with other portions of the TCE table and are therefore easier to allocate within the real address space.
"In at least one embodiment, a configurable TCE data structure is implemented that can be configured to employ one or more levels of TCE tables to hold TCEs for translating between the I/O address space and real address space of a data processing system.
BRIEF DESCRIPTION OF THE DRAWINGS
"FIG. 1 is a high level block diagram of an exemplary data processing system in accordance with one embodiment;
"FIG. 2 is a logical view of a data processing system showing the hardware and software resources of the data processing system partitioned into multiple concurrently executing logical partitions (LPARs);
"FIG. 3 illustrates an I/O subsystem that provides I/O resource isolation in a data processing system in accordance with one embodiment;
"FIG. 4A depicts a conventional Peripheral Component Interconnect (PCI) host bridge (PHB);
"FIG. 4B illustrates a conventional Translation and Validation Entry (TVE) of a Translation and Validation Table (TVT) in the PHB of FIG. 4A;
"FIG. 5A depicts an improved Peripheral Component Interconnect (PCI) host bridge (PHB) in one exemplary embodiment;
"FIG. 5B illustrates an improved Translation and Validation Entry (TVE) of a Translation and Validation Table (TVT) in the PHB of FIG. 5A;
"FIG. 6 depicts a high level logical flowchart of an exemplary method of implementing a configurable TCE data structure that can be configured to implement one or more levels of TCE tables in accordance with one embodiment;
"FIG. 7 is a high level logical flowchart of an exemplary process by which a PHB handles a DMA message in accordance with one embodiment;
"FIG. 8 is a high level logical flowchart of an exemplary process by which a PHB translates an I/O address in accordance with one embodiment; and
"FIG. 9 illustrates the translation of an I/O address to a real memory address by reference to a multi-level TCE data structure in accordance with one embodiment."
For more information, see this patent application:
Keywords for this news article include: Patents, Information Technology, Information and Data Processing, Information and Data Architecture.
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