News Column

Researchers Submit Patent Application, "Stand Alone Multi-Cell Probe Card for At-Speed Functional Testing", for Approval

May 28, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors CHUNG, MENG-HSIU (Kaohsiung City, TW); Lai, Hung-Wei (Kaohsiung City, TW), filed on October 19, 2013, was made available online on May 15, 2014.

The patent's assignee is Hermes Testing Solutions Inc.

News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates to a semiconductor device testing at wafer level stage, and more particular to a method and an apparatus of stand along muti-cell probe card with high speed testing capability.

"The conventional semiconductor testing requires a system consisted of ATE (Auto Test Equipment) and probers or handlers. The signal traveling paths from ATE/test head to PIB (Probe Interface Board) or Load board then connected to probe card or socket head via pogo blocks or other type of connector. Too many junctions (such as impedance discontinuity) are introduced. This kind of combination not only degrades DUT (Device Under Testing) running speed but also adds more loading of inputs and outputs.

"ATE providers submit an improvement way subsequently called Direct docking which integrated the probe card PCB with Probe interface board in one level, similar to a high performance Load board applied on package testing. Both of the scenarios of F/T (final testing) and C/P (circuit probing) with same paces as below: 1)Test Head/ PE cards; 2) Docking of Prober (Handler); 3) Probe interface board (Load board); 4) Probe head (Socket); 5) Probe community (Pin group); and 6) Die/wafer (Package).

"In general, scan tests performed by existing ATE systems take place at a slow speed, normally with a 10 MHz-100 MHz clock rate. The loose timing requirements imposed by these systems have an adverse effect on the overall speed of the testing protocol, and even on the accuracy of the results. In order to achieve scan test results that keep up with production demands, the solution is to increase ATE resources, such as increasing the scan band width, or simply to reconstruct the existing ATE overall system structure with one that has more resource capabilities for the implementation of the scan test. This approach unduly increases the cost of the test system and drives up the cost of production.

"It is therefore there is a need of testing equipment capable of providing a solution for Semiconductor device testing at wafer level stage with most high speed demanding and lower the usage of interconnectors in-between the test head, probe interface board (HiFix), pogo card (tower) and probe card PCB."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "The present invention is directed to a semiconductor device testing at wafer level stage, and more particular to a method and an apparatus of stand along muti-cell probe card with high speed testing capability, and with the low cost (having minimum ICs, components modules and power consumption), high speed (with shortest paths) and high throughput (with high parallel count of DUT (Device Under Testing)).

"In one embodiment of the invention, a probe card comprising a printed circuit board with at least two connection arrangements thereon and a daughter board connecting to the printed circuit board through one of the connection arrangements is provided. The daughter board comprises a plurality of cell modules, each cell modules has a socket for receiving a device under test, wherein each of the connection arrangements of the printed circuit board is for connecting each of predetermined daughter boards respectively.

"In another embodiment of the invention, a probe card comprising a printed circuit board with a plurality of connection arrangements thereon and a daughter board connecting to the printed circuit board through one of the connection arrangements is provided. The daughter board comprises a plurality of cell modules, each cell modules has a socket for receiving a device under test, a plurality of circuit boards with vertically attached on the daughter board surrounding the socket, each the circuit board has a memory unit and a power unit thereon. Each of the connection arrangements of the printed circuit board is for connecting each of predetermined daughter boards respectively.

"In still another embodiment of the invention, auto test equipment comprises a test head with a probe card is provided. The probe card comprises a printed circuit board with at least two connection arrangements thereon and a daughter board connecting to the printed circuit board through one of the connection arrangements. The daughter board comprises a plurality of cell modules, each cell modules has a socket for receiving a device under test, wherein each of the connection arrangements of the printed circuit board is for connecting each of predetermined daughter boards respectively.

BRIEF DESCRIPTION OF THE DRAWINGS

"The foregoing conceptions and their accompanying advantages of this invention will become more readily appreciated after being better understood by referring to the following detailed description, in conjunction with the accompanying drawings, wherein:

"FIG. 1 shows an exploded view of a probe card according to one embodiment of the present invention;

"FIG. 2 shows an exploded view of a probe card according to another embodiment of the present invention;

"FIG. 3 shows an exploded view of a probe card according to another embodiment of the present invention;

"FIG. 4 shows a top view of a printed circuit board according to one embodiment of the present invention; and

"FIG. 5 shows a top view of a subsidiary board according to one embodiment of the present invention.

"FIG. 6 is a schematic diagram showing the internal assembly according to an embodiment of the present invention;

"FIG. 7 is a schematic diagram showing the inner of the subsidiary board according to the present invention;

"FIG. 8 is a schematic cross sectional view of the cell module and the subsidiary board of the present invention;

"FIG. 9 is an enlarged view of cross sectional view of the cell module, especially showing the FPGA socket of the cell module of the present invention;

"FIG. 10 shows an embodiment of the cell module which is 3 by 3 arrangement;

"FIG. 11 shows the embodiment of the cell module which is 3 by 3 arrangement in detail;

"FIG. 12 shows another embodiment of the cell module which is 4 by 4 arrangement in detail;

"FIG. 13 depicts a schematic cross sectional view of the assembly of the present invention when the each FPGA is received in the FPGA socket for testing the DUT;"

For additional information on this patent application, see: CHUNG, MENG-HSIU; Lai, Hung-Wei. Stand Alone Multi-Cell Probe Card for At-Speed Functional Testing. Filed October 19, 2013 and posted May 15, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4852&p=98&f=G&l=50&d=PG01&S1=20140508.PD.&OS=PD/20140508&RS=PD/20140508

Keywords for this news article include: Electronics, Circuit Board, Semiconductor, Hermes Testing Solutions Inc..

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Source: Electronics Newsweekly