News Column

Patent Issued for Semiconductor Device, Test Method, and Test Apparatus

May 28, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventor Choi, Young-Don (Seoul, KR), filed on October 11, 2011, was published online on May 13, 2014.

The patent's assignee for patent number 8723529 is Samsung Electronics Co., Ltd. (Suwon-si, Gyeonggi-do, KR).

News editors obtained the following quote from the background information supplied by the inventors: "The present inventive concept relates to semiconductor devices, methods of testing semiconductor devices, and associated test apparatuses.

"During testing various constituent circuits and elements of a semiconductor device will be evaluated in response to one or more test signals. Such test signals are generally provide by an external source (e.g., a controller, tester, or connected test equipment). A test signal may be voltage or a current. A test voltage may be simultaneously applied in parallel to a plurality of semiconductor devices. However, a test current must usually be applied to semiconductor devices in a point-to-point manner. That is, the test current must be individually applied to respective semiconductor devices. This limitation results in lengthy test times and/or very costly test equipment setups. Given the vast number of semiconductor devices that must effectively tested before commercial shipment, manufacturers seek to reduce per device test times to an absolute minimum, consistent with test reliability."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventor's summary information for this patent: "Embodiments of the inventive concept provide semiconductor devices that may be collectively tested in parallel using a test current.

"In one embodiment, the inventive concept provides a semiconductor device comprising; a first pad that receives an external voltage during a test, a second pad coupled to an external impedance during the test, a voltage-current converter coupled to the first pad and the second pad and configured to generate a bias current substantially in response to only the external voltage and the external impedance, and an internal circuit responsive to a test current during the test, wherein a level of the test current is defined by a level of the bias current.

"In another embodiment, the inventive concept provides a semiconductor device comprising; a first pad that receives an external voltage during a test, a second pad that is coupled to an external impedance during the test, a voltage-current converter coupled to the first pad and the second pad and configured to generate a bias current substantially in response to only the external voltage and the external impedance, and an internal circuit responsive to a test current during the test, wherein a level of the test current is defined by a level of the bias current, wherein the voltage-current converter comprises; a driving transistor coupled between ground and the second pad and configured to generate the bias current in response to a bias voltage, and a comparator having inputs respectively coupled to the first pad and the second pad, having an output coupled to the gate of the driving transistor, and configured to generate the bias voltage at the output by comparing the external voltage with a reference voltage apparent at the second pad.

"In another embodiment, the inventive concept provides a method of testing semiconductor devices. The method comprises; arranging a plurality of semiconductor devices for a test designed to apply a test current to an internal circuit of each one of the plurality of semiconductor devices, wherein each one of the plurality of semiconductor devices includes a first pad, a second pad, and a voltage-current converter coupled to the first pad and the second pad, applying an external voltage to the first pads of the plurality of semiconductor devices, coupling an external impedance to the second pads of the plurality of semiconductor devices, and generating a bias current substantially in response to only the external voltage and the external impedance within the voltage-current converter of each one of the plurality of semiconductor devices, wherein a level of the test current is defined by the bias current."

For additional information on this patent, see: Choi, Young-Don. Semiconductor Device, Test Method, and Test Apparatus. U.S. Patent Number 8723529, filed October 11, 2011, and published online on May 13, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=69&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=3412&f=G&l=50&co1=AND&d=PTXT&s1=20140513.PD.&OS=ISD/20140513&RS=ISD/20140513

Keywords for this news article include: Semiconductor, Samsung Electronics Co. Ltd..

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Source: Electronics Newsweekly


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