News Column

Patent Issued for Power Semiconductor Device

May 28, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventor Oh, Jung Hun (Seoul, KR), filed on March 12, 2013, was published online on May 13, 2014.

The assignee for this patent, patent number 8723228, is LG Innotek Co., Ltd. (Seoul, KR).

Reporters obtained the following quote from the background information supplied by the inventors: "Power semiconductor devices are classified into Schottky barrier diodes, metal semiconductor field effect transistors, and high electron mobility transistors (HEMTs).

"An HEMT is widely used due to excellent electron mobility and low noise characteristics thereof as an integrated circuit device operating at ultra high frequencies up to millimeter wave frequencies. As application systems employing HEMTs become more complex and elaborate, characteristics, particularly, radio frequency (RF) characteristics of HEMTs need to be improved.

"Maximum oscillation frequency (F.sub.max) is a very important factor to evaluate RF characteristics of the HEMT. The maximum oscillation frequency (F.sub.max) may be improved by adjusting small-signal parameters and improving DC characteristics. There are a lot of other variables affecting the DC characteristics and small-signal parameters of the HEMT. Among these, a gate-recess structure, as the most important factor, will be described hereinafter.

"FIG. 1 is a side view, in section, schematically illustrating a conventional HEMT device 1A having a first gate-recess structure with a wide recess region where a gate electrode is disposed. FIG. 2 is a side view, in section, schematically illustrating a conventional HEMT device 1B having a second gate-recess structure with a narrow recess region where a gate electrode is disposed.

"Referring to FIGS. 1 and 2, each of the conventional HEMT devices 1A and 1B includes a substrate 10, a buffer layer 20 disposed on the substrate 10, a barrier layer 30 disposed on the buffer layer 20, and a cap layer 40 disposed on the barrier layer 3.

"The conventional HEMT devices 1A and 1B respectively include recess regions R.sub.1 and R.sub.2 formed by partially removing the cap layer 40 to expose the barrier layer 30. A gate electrode 53 is disposed in each of the recess regions R.sub.1 and R.sub.2, and a source electrode 51 and a drain electrode 52 are disposed on the cap layer 40.

"The HEMT device 1A illustrated in FIG. 1 has the first gate-recess structure with a wide recess region formed by partially removing the cap layer 40 except for regions on which the source electrode 51 and the drain electrode 52 are disposed. The HEMT device 1B illustrated in FIG. 2 has the second gate-recess structure with a narrow recess region formed by partially removing the cap layer 40 only at a region where the gate electrode 53 will be formed.

"The HEMT device 1B having the second gate-recess structure has higher maximum drain current (I.sub.dss,max) and higher maximum transconductance (G.sub.m,max) than the HEMT device 1A having the first gate-recess structure. This is because in the HEMT device 1A having the first gate-recess structure, a free surface state 40a (marked with x) formed on the surface of the barrier layer 30 exposed by the recess region R.sub.1 exhibits a negatively charged surface state to change the field in a channel 21, thereby reducing sheet carrier density (n.sub.s).

"Meanwhile, RF characteristics of the HEMT device 1B having the second gate-recess structure have not been improved compared to those of the HEMT device 1A having the first gate-recess structure although the HEMT device 1B has excellent DC characteristics. This is because the cap layer 40 with conductivity is formed up to the vicinity of the gate electrode 53 in the HEMT device 1B having the second gate-recess structure to reduce a substantial distance between the gate electrode and the drain electrode, thereby increasing capacitance (C.sub.gd) between the gate electrode and the drain electrode. Since influence of small-signal parameters on RF characteristics is relatively low compared to that of capacitance (C.sub.gd) between the gate electrode and the drain electrode on RF characteristics, description has focused on capacitance (C.sub.gd).

"Thus, there is a need to develop a power semiconductor having excellent DC characteristics and excellent RF characteristics."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventor's summary information for this patent: "Embodiments provide a power semiconductor device.

"In one embodiment, a power semiconductor device includes a substrate, a first semiconductor layer disposed on the substrate, a second semiconductor layer disposed on the first semiconductor layer, a third semiconductor layer disposed on the second semiconductor layer and exposing a portion of the second semiconductor layer, a gate electrode disposed on the portion of the second semiconductor layer exposed via the third semiconductor layer, and a source electrode and a drain electrode disposed on the third semiconductor layer at both sides of the gate electrode to be spaced apart from each other. An electrical segregation region is formed in the third semiconductor layer between the gate electrode and the drain electrode.

"The electrical segregation region may be disposed adjacent to the drain electrode.

"The gate electrode may contact the second semiconductor layer.

"The electrical segregation region may be formed in the third semiconductor layer extending to a portion of the second semiconductor layer.

"A channel layer may be disposed at an interface of the first semiconductor layer contacting the second semiconductor layer, and the electrical segregation region may be spaced apart from the channel layer.

"A width of the portion of the second semiconductor layer exposed through the third semiconductor layer may correspond to a length of the gate electrode.

"A portion of the gate electrode connected to the second semiconductor layer may have a smaller width than that the opposite portion of the gate electrode.

"The second semiconductor layer may have a recess portion, and the gate electrode may be disposed on the recess portion.

"The recess portion may correspond to the portion of the second semiconductor layer exposed via the third semiconductor layer.

"A passivation layer may be disposed on the third semiconductor layer.

"An ion implanted into the electrical segregation region may have a different conductivity type than the conductivity type of the third semiconductor layer.

"A thickness of the electrical segregation region disposed in the second semiconductor layer may be less than a thickness of the entire second semiconductor layer.

"The electrical segregation region may include at least one of Mg, Zn, Ca, Sr, Ba, Fe, or Ar.

"In another embodiment, a power semiconductor device includes a source electrode, a drain electrode, and a gate electrode disposed between the source electrode and the drain electrode, a third semiconductor layer disposed under the source electrode and the drain electrode and having an open region with a width corresponding to a length of the gate electrode, a second semiconductor layer disposed under the third semiconductor layer and connected to the gate electrode through the open region, and a first semiconductor layer disposed under the second semiconductor layer. The third semiconductor layer includes a first region disposed adjacent to the gate electrode, a second region disposed adjacent to the drain electrode, and a third region disposed between the first region and the second region, and the third region electrically separates the first region from the second region.

"The third region may be an electrical segregation region into which an ion having a different conductivity type from the conductivity type of the third semiconductor layer is implanted.

"The third region may be disposed adjacent to the drain electrode.

"The power semiconductor device may further include a substrate disposed under the first semiconductor layer, and a transition layer disposed between the substrate and the first semiconductor layer.

"The third region may include at least one of Mg, Zn, Ca, Sr, Ba, Fe, or Ar.

"The second semiconductor layer may have a recess portion, and the gate electrode may be disposed on the recess portion.

"In another embodiment, a power semiconductor device includes a substrate, a first semiconductor layer disposed on the substrate, a second semiconductor layer disposed on the first semiconductor layer, a third semiconductor layer disposed on the second semiconductor layer and exposing a portion of the second semiconductor layer, a gate electrode disposed on the portion of the second semiconductor layer exposed via the third semiconductor layer, and a source electrode and a drain electrode disposed on the third semiconductor layer at both sides of the gate electrode to be spaced apart from each other. A portion of the third semiconductor layer adjacent to the gate electrode is electrically separated from another portion of the third semiconductor layer adjacent to the drain electrode between the gate electrode and the drain electrode."

For more information, see this patent: Oh, Jung Hun. Power Semiconductor Device. U.S. Patent Number 8723228, filed March 12, 2013, and published online on May 13, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=75&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=3708&f=G&l=50&co1=AND&d=PTXT&s1=20140513.PD.&OS=ISD/20140513&RS=ISD/20140513

Keywords for this news article include: Electronics, Semiconductor, LG Innotek Co. Ltd..

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Source: Electronics Newsweekly


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