The Cadence Denali DDR4 IP solution consists of a DDR PHY and controller that have been verified in silicon for interoperability. The solution supports high-performance systems, including several unique features such as per-bit de-skew capability and low-jitter phase-locked loops (PLLs). Additionally, its compatibility to DDR3 and DFI 3.1 standards ensures interoperability with other IP and allows for multiple memory types to be used within the same design.
The Cadence HSIC PHY IP is a complete mixed-signal transceiver macro-cell that implements the USB 2.0 HSIC layer for USB 2.0 high-speed device and host applications. The integrated solution made up of the Cadence HSIC PHY interface with the STMicroelectronics HSIC PHY I/O features extremely low power consumption and silicon area.
Cadence also announced the qualification of its digital implementation, signoff and custom/analog design tools for the 28nm FD-SOI process, including Cadence Encounter Digital Implementation System, Interactive Physical Verification System, QRC Extraction Solution, Tempus(TM) Timing Signoff Solution, Spectre Simulator, Virtuoso Schematic Editor, Virtuoso Analog Design Environment, and Virtuoso Layout Suite.
"Companies looking to take advantage of the performance and power benefits of 28nm FD-SOI need to know that they also have the IP solutions and tools that are qualified for the process," stated
"FD-SOI technology delivers superior energy efficiency at the 28nm node and allows for a wider range of dynamic voltage and frequency scaling, leading to higher processing power per watt, lower thermal dissipation, and extended battery life for portable devices," said Philippe Magarshack, executive vice president, Design Enablement and Services,
For more information on the Cadence Denali DDR4 IP, visit www.cadence.com/news/ddr4ip .
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