News Column

Researchers Submit Patent Application, "Efficient Scan Latch Systems and Methods", for Approval

May 22, 2014



By a News Reporter-Staff News Editor at Politics & Government Week -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Elkin, Ilyas (Sunnyvale, CA); Yang, Ge (Dublin, CA), filed on October 29, 2012, was made available online on May 8, 2014.

The patent's assignee is Nvidia Corporation.

News editors obtained the following quote from the background information supplied by the inventors: "Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems have facilitated increased productivity and reduced costs in analyzing and communicating data in most areas of business, science, education and entertainment. The manner in which the electronic devices perform operations can have a significant impact on performance and end results and testing device performance is often important. However, conventional approaches to testing component operations can have many limitations and can be very complex and complicated.

"Traditional scan flip flops are used in many kinds of integrated circuits for various testing purposes (e.g., in order to test chips for defects). The traditional approaches often use inputs derived by automatic test pattern generation (ATPG). Both tester time and test escapes which are packaged and later discarded present a significant cost to integrated circuit manufacturers. Some traditional approaches attempt to mitigate this by adding test features to chips to enable quick and reliable testing. In a modern processor, that often means that a majority of flip flops have scan features, which typically allows ATPG patterns to be shifted in from flip-flop to flip-flop in order to provide inputs for test and then captured test results to be shifted out for comparison with expected values. In some conventional mux-scan methods, scan testing utilizes a scan mux in the flip flop, which typically selects either between data input in functional mode or scan input in scan shift mode, based on a scan enable signal acting as a select. FIG. 1A is a block diagram of a prior art scan latch system. FIG. 1 B is an illustration of a prior art scan master slave flip flop approach utilizing the master latch system of FIG. 1A. FIG. 2A is a block diagram of another prior art scan latch system with gated clock. FIG. 2B is an illustration of another prior art scan master slave flip flop approach utilizing the master latch system of FIG. 2A.

"In recent years there has been an increased focus on power consumption and some conventional approaches try to reduce the usage of high power fast dynamic and sense amplifier flip flops in favor of static flip flops. However, static master slave flip flops are usually slower than dynamic topologies and there has been increased focus on improving the speed of static flip flops so they can better serve as replacements to dynamic and sense amplifier flip flops in critical paths. In some prior art designs, the select to the scan mux are gated by a clock (e.g., to take the clocked transmission gate out of the critical path) in an attempt to improve speed. In those prior art designs, the scan multiplexor is still put in the critical data path of the flip flop, which adds extra diffusion and parasitic loads to the critical path, typically resulting in additional delay overhead for the flip flop, even when the flip flop is not used for scan."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value (SI) and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component.

DESCRIPTION OF THE DRAWINGS

"The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention by way of example and not by way of limitation. The drawings referred to in this specification should be understood as not being drawn to scale except if specifically noted.

"FIGS. 1A and 1B are illustrations of one prior art scan latch system, and a corresponding prior art master slave flip flop approach, respectively.

"FIGS. 2A and 2B are illustrations of another prior art scan latch system with gated clock, and a corresponding prior art master slave flip flop approach, respectively.

"FIG. 3 is a block diagram of an exemplary scan latch system in accordance with one embodiment of the present invention.

"FIG. 4 is an exemplary scan latch method in accordance with one embodiment of the present invention.

"FIG. 5 is a block diagram of exemplary master slave scan flip flop in accordance with one embodiment of the present invention.

"FIG. 6 is a block diagram of exemplary master slave scan flip flop in accordance with one embodiment of the present invention.

"FIG. 7 is a block diagram of exemplary master slave scan flip flop with a gated clock in accordance with one embodiment of the present invention.

"FIG. 8 is a block diagram of exemplary master slave scan flip flop in accordance with one embodiment of the present invention.

"FIG. 9 is a block diagram of an exemplary scan latch system in accordance with one embodiment of the present invention.

"FIG. 10 is a block diagram of an exemplary low phase scan latch in accordance with one embodiment of the present invention.

"FIG. 11 is a block diagram of an exemplary low phase scan latch with a gated clock used to select between a scan in and a recirculate value in accordance with one embodiment of the present invention.

"FIG. 12 is a block diagram of an exemplary high phase scan latch in accordance with one embodiment of the present invention.

"FIG. 13 is a block diagram of an exemplary high phase scan latch with a gated clock used to select between a scan in and a recirculate value in accordance with one embodiment of the present invention."

For additional information on this patent application, see: Elkin, Ilyas; Yang, Ge. Efficient Scan Latch Systems and Methods. Filed October 29, 2012 and posted May 8, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=411&p=9&f=G&l=50&d=PG01&S1=20140501.PD.&OS=PD/20140501&RS=PD/20140501

Keywords for this news article include: Nvidia Corporation.

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Source: Politics & Government Week