News Column

Patent Issued for Multi-Chip Package

May 21, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Kim, Ki Young (Seongnam-si, KR); Park, Myung Gun (Seoul, KR), filed on November 30, 2012, was published online on May 6, 2014.

The assignee for this patent, patent number 8716854, is SK Hynix Inc. (Gyeonggi-do, KR).

Reporters obtained the following quote from the background information supplied by the inventors: "The present invention generally relates to a semiconductor package, and more particularly, to a multi-chip package which has a novel shape capable of accomplishing light weight, thinness, compactness, and miniaturization.

"In a semiconductor package, in order to increase capacity and extend functionality, a degree of integration is being gradually increased in a wafer state. Further, a semiconductor package in which at least two kinds of semiconductor chips or semiconductor packages are incorporated is being generalized.

"In order to extend the functionality of a semiconductor device in a wafer state, substantial equipment investment is needed in a wafer manufacturing process, a lot of costs are incurred, and various problems likely to occur in processing should be solved first. However, incorporating at least two semiconductor chips or at least two semiconductor packages into one package in the course of assembling semiconductor chips into a semiconductor package after manufacturing the semiconductor chips may be realized without requiring prior settlements as described above. Further, when compared to increasing capacity and extending functionality in a wafer state, since the incorporation requires a lesser degree of equipment investment and does not incur a lot of costs, semiconductor device manufacturers have actively conducted search for incorporated type semiconductor packages such as a system-in-package (SIP), a multi-chip package (MCP) and a package-on-package (POP).

"Among these incorporated type semiconductor packages, the multi-chip package is manufactured by incorporating at least two packages with different functionalities into one package. In an example of the multi-chip package, a structure is used, in which a plurality of memory chips are stacked on a substrate, a controller chip is stacked on the stacked memory chips, and the memory chips and the substrate and the controller chip and the substrate are electrically connected using wires.

"Nevertheless, even in such a multi-chip package, the thickness of the package increases due to the presence of the controller chip stacked on the memory chips, and the wires for connecting the controller chip and the substrate are likely to short-circuit with the wires connected with the memory chips. In order to prevent the wires connected with the controller chip and the wires connected with the memory chips from short-circuiting, the wires connecting the controller chip and the substrate should be formed long. Thus, a design is complicated, the size of the package increases, and a fail such as wire sweeping and wire damage is likely to occur in a molding process."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "An embodiment is directed to a multi-chip package which has a novel shape capable of accomplishing light weight, thinness, compactness and miniaturization.

"In an embodiment, a multi-chip package includes: a main substrate; a plurality of first semiconductor chips stacked on an upper surface of the main substrate and having bonding pads which are electrically connected with the main substrate; and a semiconductor package attached to side surfaces of the stacked first semiconductor chips and electrically connected with the main substrate.

"The semiconductor package may include: a sub substrate including a mounting part which is attached to the side surfaces of the stacked first semiconductor chips and has first pads, and a connection part which is bent and extends from the mounting part, is placed on the upper surface of the main substrate and has second pads electrically connected with the first pads and the main substrate; and a second semiconductor chip disposed on the other surface of the mounting part facing away from one surface of the mounting part which is attached to the side surfaces of the stacked first semiconductor chips, and having bonding pads electrically connected with the first pads.

"The multi-chip package may further include a fixing member formed between the connection part and the main substrate and fixing the connection part and the main substrate to each other.

"The sub substrate may include any one of a flexible substrate, a silicon substrate and a lead frame substrate.

"The first semiconductor chips and the second semiconductor chip may be different kinds of chips. For example, the first semiconductor chips may be memory chips and the second semiconductor chip may be a controller chip.

"The main substrate may further have a groove in which the semiconductor package is fitted. In this case, the semiconductor package may include: a sub substrate including a mounting part which is attached to the side surfaces of the stacked first semiconductor chips and has first pads, and a connection part which extends from the mounting part, is fitted into the groove of the main substrate and has second pads electrically connected with the first pads and the main substrate; and a second semiconductor chip disposed on the other surface of the mounting part facing away from one surface of the mounting part which is attached to the side surfaces of the stacked first semiconductor chips, and having bonding pads electrically connected with the first pads.

"The multi-chip package may further include connection members electrically connecting the bonding pads of the first semiconductor chips and the main substrate. Additionally, the respective first semiconductor chips may further have through electrodes which are electrically connected with the bonding pads, and the first semiconductor chips may be stacked on the main substrate such that the through electrodes are connected with one another and are electrically connected with the main substrate.

"The first semiconductor chips may be vertically stacked such that the side surfaces of the first semiconductor chips are aligned, and the semiconductor package may be attached to the aligned side surfaces of the first semiconductor chips.

"The first semiconductor chips may be stacked in substantially a step-like shape such that the bonding pads are exposed. In this case, each of the first semiconductor chips may have a step surface which faces a main substrate, on the other end thereof facing away from one end on which the bonding pads are disposed, and the semiconductor package may be attached to the step surfaces of the first semiconductor chips and side surfaces of the first semiconductor chips which are connected with the step surfaces.

"The multi-chip package may further include a second adhesive member attaching the side surfaces of the first semiconductor chips and the semiconductor package to each other. Besides, The multi-chip package may further include a molding part sealing the upper surface of the main substrate including the first semiconductor chips and the semiconductor package.

"The multi-chip package further includes a molding part sealing the upper surface of the main substrate including the first semiconductor chips and the semiconductor package. The molding part comprises an epoxy molding compound.

"The first semiconductor chip includes a circuit block. The multi-chip package further includes a bonding pad formed on a one surface of the semiconductor chip, the bonding pad configured to be used as an electrical contact for the circuit block of the semiconductor chip. The main substrate is a printed circuit board."

For more information, see this patent: Kim, Ki Young; Park, Myung Gun. Multi-Chip Package. U.S. Patent Number 8716854, filed November 30, 2012, and published online on May 6, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=73&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=3619&f=G&l=50&co1=AND&d=PTXT&s1=20140506.PD.&OS=ISD/20140506&RS=ISD/20140506

Keywords for this news article include: Electronics, SK Hynix Inc., Semiconductor.

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Source: Electronics Newsweekly