News Column

"Semiconductor Package" in Patent Application Approval Process

May 21, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent application by the inventors LEE, Sang Eun (Icheon-si, KR); RYU, Sung Soo (Seongnam-si, KR); KIM, Chang Il (Busan, KR); JEON, Seon Kwang (Icheon-si, KR), filed on March 13, 2013, was made available online on May 8, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application is assigned to Sk Hynix Inc.

The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention generally relates to a semiconductor package, and more particularly, to a semiconductor package which has a novel shape featuring a light, thin, compact, and miniaturized structure.

"The technology industry has provided products that feature light weight, miniaturization, and multi-functionality. One way this has been provided has been through a semiconductor package that incorporates a driving chip and a memory chip constructed in one module. Furthermore, the driving chip and the memory chip are fabricated as separate packages, and are either vertically or horizontally mounted on a mother board.

"FIGS. 1 and 2 are cross-sectional views illustrating conventional semiconductor packages. FIG. 1 is a cross-sectional view illustrating a structure in which a driving package 10 and a memory package 20 are vertically stacked, and FIG. 2 is a cross-sectional view illustrating a structure in which a driving package 10 and a memory package 20 are horizontally mounted on a mother board 30.

"However, when the driving package 10 and the memory package 20 are vertically stacked, a signal transfer path between the driving package 10 and the memory package 20 grows physically and in complexity which may cause problems, and when the driving package 10 and the memory package 20 are horizontally mounted on the mother board 30, the occupancy area of the mother board 30 increases, thereby adding difficulty to meet miniaturization demands.

"Within the memory package 20, in order to realize a product that features a memory capacity capable of holding twice as much information compared to that of a single-chip memory, at least two memory chips 2 are stacked and connected with a substrate 3 via wires W. Subsequently, in order to protect the memory package 20, a molding part 5 is formed to seal the upper surface of the substrate 3 and the stacked memory chips 2.

"Since wires W may have loops for preventing short-circuiting with peripheral components of the memory chips 2, the size of the memory package 20 increases due to the presence of the wire loops, which goes against the efforts of miniaturization. Also, a spacer 4 may be additionally formed between the stacked memory chips 2 to secure the height of the wire loops. As the number of stacked memory chips 2 increases, the height of the wire loops which are formed on the upper surface of the memory chip accordingly increases, thereby causing limitations in the number of memory chips 2 to be stacked. Moreover, as the number of stacked memory chips 2 increases, the length of wires W accordingly increases, which may cause problems such as wire sweeping, wire damage, and short-circuiting between peripheral components of the memory chips 2 and the wires W during a process for forming the molding part 5. In addition, since the wires W may be formed using gold, the package fabrication cost may substantially increase. In a memory chip such as a DRAM, which is fabricated to have a center pad structure, redistribution lines may be additionally formed to redistribute bonding pads to an edge of a chip for wire bonding, adding further complexity to the process. When grinding the memory chips 2 as thin as possible, although the number of memory chips 2 to be stacked may increase, failures such as warpage and cracking is likely to occur."

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "Various embodiments are directed to a semiconductor package which has a novel shape featuring a light, thin, compact, and miniaturized structure.

"In an embodiment, a semiconductor package may include: a first substrate, a plurality of memory chips horizontally disposed on the first substrate, and having one surfaces which face the first substrate, other surfaces which face away from the one surfaces, and first bumps formed on the other surfaces, a second substrate disposed on the plurality of memory chips and electrically connected with the first bumps, a sub-substrate horizontally disposed on the first substrate together with the plurality of memory chips and electrically connecting the first substrate and the second substrate, and a driving chip having second bumps on one surface thereof and mounted to the second substrate such that the second bumps are electrically connected with the second substrate.

"The plurality of memory chips may be constituted by the same kind of memory chips which have substantially similar structures, and may be constituted by at least two kinds of memory chips which have different structures.

"The plurality of memory chips may be disposed in a matrix manner when viewed in plan view, and the plurality of memory chips may have major axes aligned parallel to each other. Further, the sub-substrate may be disposed in a direction of the major axes of the memory chips when viewed in plan view, or alternatively, may be disposed in a direction of minor axes of the memory chips when viewed in plan view.

"The plurality of memory chips and the sub-substrate may be disposed in a matrix manner when viewed in plan view.

"The semiconductor package may further include adhesive members attaching the first substrate and the plurality of memory chip to each other. The semiconductor package may further include: a molding part sealing an upper surface of the first substrate and encompassing the memory chips, the second substrate, the driving chip, and external connection terminals mounted to a lower surface of the first substrate.

"The semiconductor package may further include additional memory chips stacked on the first substrate, such as memory chips which belong in a different kind. For example, the memory chips may include DRAM devices, and the additional memory chips may include flash memory devices. Moreover, the semiconductor package may further include wires electrically connecting bonding pads of the additional memory chips with the first substrate, and the additional memory chips may be stacked in a step-like shape such that their bonding pads are exposed. Each of the additional memory chips may have through vias, and may be stacked such that their through vias are connected with one another.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIGS. 1 and 2 are cross-sectional views illustrating conventional semiconductor packages.

"FIG. 3 is a cross-sectional view illustrating a semiconductor package in accordance with a first embodiment of the present invention.

"FIG. 4 is a plan view illustrating the memory chips, the sub-substrate, and the first substrate of FIG. 3.

"FIG. 5 is a plan view illustrating a semiconductor package in accordance with a second embodiment of the present invention.

"FIG. 6 is a plan view illustrating a semiconductor package in accordance with a third embodiment of the present invention.

"FIG. 7 is a plan view illustrating a semiconductor package in accordance with a fourth embodiment of the present invention.

"FIG. 8 is a plan view illustrating a semiconductor package in accordance with a fifth embodiment of the present invention.

"FIG. 9 is a cross-sectional view taken along the line I-I' of FIG. 8.

"FIG. 10 is a cross-sectional view illustrating a semiconductor package in accordance with a sixth embodiment of the present invention.

"FIG. 11 is a perspective view illustrating an electronic apparatus having a semiconductor package according to various embodiments of the present invention.

"FIG. 12 is a block diagram showing an example of the electronic apparatus having a semiconductor package according to various embodiments of the present invention."

URL and more information on this patent application, see: LEE, Sang Eun; RYU, Sung Soo; KIM, Chang Il; JEON, Seon Kwang. Semiconductor Package. Filed March 13, 2013 and posted May 8, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=5928&p=119&f=G&l=50&d=PG01&S1=20140501.PD.&OS=PD/20140501&RS=PD/20140501

Keywords for this news article include: Electronics, Sk Hynix Inc, Semiconductor.

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Source: Electronics Newsweekly


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