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Researchers Submit Patent Application, "Semiconductor Structure Incorporating a Contact Sidewall Spacer with a Self-Aligned Airgap and a Method of...

May 21, 2014



Researchers Submit Patent Application, "Semiconductor Structure Incorporating a Contact Sidewall Spacer with a Self-Aligned Airgap and a Method of Forming the Semiconductor Structure", for Approval

By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Chen, Fen (Williston, VT); Gambino, Jeffrey P. (Westford, VT); He, Zhong-Xiang (Essex Junction, VT); Wang, Xin (Beacon, NY); Wang, Yanfeng (Fishkill, NY), filed on October 31, 2012, was made available online on May 8, 2014.

The patent's assignee is International Business Machines Corporation.

News editors obtained the following quote from the background information supplied by the inventors: "The present disclosure relates to semiconductor structures and, more specifically, to embodiments of a semiconductor structure that incorporates a contact sidewall spacer with a self-aligned airgap and a method of forming the semiconductor structure.

"As technology scaling continues, the size of middle of the line (MOL) contacts for semiconductor devices in advanced very large-scale integrated (VLSI) circuits is shrinking, leading to increased parasitic resistance. The minimum dielectric spacing between a contact and other conductive semiconductor device components (e.g., the minimum dielectric spacing between a source/drain region contact and a gate structure in the case of a field effect transistor (FET)) is also shrinking, leading to an increase parasitic capacitance as well as a corresponding increase in the probability of a short. The increases in parasitic resistance, parasitic capacitance and the probability of a short, in turn, impact semiconductor device performance and reliability. Additionally, rapid adoptions of new device component materials (e.g., in the case of FETs, rapid adoptions of metal gate conductors, epitaxial silicon germanium (SiGe) source/drain regions, copper contacts, etc.) and rapid adoptions of new device configurations (e.g., in the case of FETs, rapid adoptions of raised source/drain regions, stress layers, fin-type semiconductor bodies, etc.) have further exacerbated these issues. Unfortunately, since an increase in contact size decreases parasitic resistance, but also increases parasitic capacitance and the probability of a short for a semiconductor device of a given size because of the corresponding decrease in dielectric spacing, and since an increase in dielectric spacing decreases parasitic capacitance and the probability of a short, but also increases parasitic resistance for a semiconductor device of a given size because of the corresponding decrease in contact size, semiconductor device design typically involves a trade-off between contact size and dielectric spacing."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "In view of the foregoing, disclosed herein are embodiments of a semiconductor structure that optimizes semiconductor device performance and reliability by incorporating a contact sidewall spacer with a self-aligned airgap. Specifically, the semiconductor structure can comprise a semiconductor device (e.g., a two-terminal semiconductor device, such as a PN junction diode or Schottky diode, or a three-terminal semiconductor device, such as a field effect transistor (FET), a bipolar junction transistor (BJT), a thrysistor, etc.) and a dielectric layer that covers the semiconductor device. A contact can extend vertically through the dielectric layer to a terminal of the semiconductor device (e.g., in the case of a FET, to a source/drain region of the FET). A contact sidewall spacer can be positioned laterally adjacent to the contact sidewall and can incorporate an airgap. Since air has a lower dielectric constant than other typically used dielectric spacer or interlayer dielectric materials, the contact size can be increased for reduced parasitic resistance while minimizing corresponding increases in parasitic capacitance or the probability of shorts. Also disclosed herein are embodiments of a method of forming such a semiconductor structure.

"More particularly, disclosed herein are embodiments of a semiconductor structure. Generally, the semiconductor structure can comprise a semiconductor device. The semiconductor device can comprise any type of semiconductor device having contacted terminals including, but not limited to, a two-terminal semiconductor device (e.g., diode, such as a PN junction diode or a Schottky diode) or a three-terminal semiconductor device (e.g., a transistor, such as a field effect transistor (FET) or a bipolar junction transistor (BJT), or a thrysistor). The semiconductor structure can further comprise a dielectric layer covering the semiconductor device and a contact having a sidewall and extending vertically through the dielectric layer to the semiconductor device and, particularly, to a terminal of the semiconductor device. Finally, the semiconductor structure can comprise a contact sidewall spacer positioned laterally adjacent to the contact sidewall and comprising an airgap. For example, the contact sidewall spacer can comprise an airgap and a dielectric liner, which is positioned laterally between the airgap and the sidewall. Alternatively, the contact sidewall spacer can comprise an airgap, which is positioned laterally adjacent to a lower portion of the contact sidewall, and a dielectric cap, which is above the airgap and positioned laterally adjacent to an upper portion of the sidewall.

"In one particular embodiment, the semiconductor structure can comprise a field effect transistor (FET). This FET can comprise a semiconductor body and a gate structure. The semiconductor body can comprise a channel region and a source/drain region adjacent to the channel region and the gate structure can be positioned on the semiconductor body adjacent to the channel region. The semiconductor structure can further comprise a dielectric layer covering the FET and a contact having a sidewall and extending vertically through the dielectric layer to the FET and, particularly, to a terminal of the FET (e.g., to the source/drain region). Finally, the semiconductor structure can comprise a contact sidewall spacer positioned laterally adjacent to the contact sidewall and comprising an airgap. For example, the contact sidewall spacer can comprise an airgap and a dielectric liner, which is positioned laterally between the airgap and the contact sidewall. Alternatively, the contact sidewall spacer can comprise an airgap, which is positioned laterally adjacent to a lower portion of the contact sidewall, and a dielectric cap, which is above the airgap and positioned laterally adjacent to an upper portion of the contact sidewall.

"Also disclosed herein are embodiments of a method of forming a semiconductor structure. Generally, the method can comprise forming a semiconductor device. The semiconductor device can comprise any type of semiconductor device having contacted terminals including, but not limited to, a two-terminal semiconductor device (e.g., diode, such as a PN junction diode or a Schottky diode) or a three-terminal semiconductor device (e.g., a transistor, such as a field effect transistor (FET) or a bipolar junction transistor (BJT), or a thrysistor). Next, the method can comprise forming a dielectric layer so as to cover the semiconductor device. Finally, the method can comprise forming a contact having a sidewall and extending vertically through the dielectric layer to the semiconductor device and, particularly, to a terminal of the semiconductor device and further forming a contact sidewall spacer positioned laterally adjacent to the contact sidewall and comprising an airgap.

"In one particular embodiment, the method can comprise forming a field effect transistor (FET). This FET can be formed so that it comprises semiconductor body and a gate structure. The semiconductor body can comprise a channel region and a source/drain region adjacent to the channel region and the gate structure can be positioned on the semiconductor body adjacent to the channel region. Next, the method can comprise forming a dielectric layer so as to cover the FET. Finally, the method can comprise forming a contact having a sidewall and extending vertically through the dielectric layer to the FET and, particularly, to a terminal of the FET (e.g., to a source/drain region) and further forming a contact sidewall spacer positioned laterally adjacent to the contact sidewall and comprising an airgap.

"In any case, the processes of forming the contact and forming the contact sidewall spacer can comprise forming an opening in the dielectric layer extending vertically to the semiconductor device and, particularly, to a terminal of the semiconductor device (e.g., in the case of a FET, to a source/drain region of the FET). Then, a sacrificial liner comprising a degradable (i.e., decomposable) material, such as a thermally degradable material or chemically degradable material, can be formed in the opening and a dielectric liner can be formed on the sacrificial liner. Next, horizontal portions of both the dielectric liner and sacrificial liner can be removed from the opening. Once the horizontal portions of both the dielectric liner and sacrificial liner are removed from the opening, a contact can be formed in the opening such that the contact has a sidewall and extends vertically through the dielectric layer to the semiconductor device. After the contact is formed in the opening, an additional dielectric layer can be formed on the dielectric layer such that it covers the opening. Finally, one or more processes can be performed in order to degrade (i.e., decompose) any remaining degradable material of the sacrificial liner, thereby forming a contact sidewall spacer comprising an airgap and a remaining vertical portion of the dielectric liner positioned laterally between the airgap and the sidewall.

"Alternatively, the processes of forming the contact and forming the contact sidewall spacer can comprise forming a first opening in the dielectric layer extending vertically to the semiconductor device and, particularly, to a terminal of the semiconductor device (e.g., in the case of a FET, to a source/drain region). Then, a sacrificial liner can be formed in the first opening and a horizontal portion of the sacrificial liner can be removed from the first opening. Once the horizontal portion of the sacrificial liner is removed from the first opening, a contact can be formed in the first opening such that the contact has a sidewall and extends vertically through the dielectric layer to the semiconductor device. After the contact is formed, a vertical portion of the sacrificial liner can be removed from the first opening so as to form a second opening, which exposes the contact sidewall. Finally, a dielectric cap can be formed in the second opening in order to form a contact sidewall spacer that comprises an airgap positioned laterally adjacent a lower portion of the contact sidewall and a dielectric cap above the airgap and positioned laterally adjacent to an upper portion of the contact sidewall.

BRIEF DESCRIPTION OF THE DRAWINGS

"The embodiments herein will be better understood from the following detailed description with reference to the drawings, which are not necessarily drawn to scale and in which:

"FIG. 1 is a diagram illustrating an embodiment of a semiconductor structure that incorporates a contact sidewall spacer with a self-aligned airgap;

"FIG. 2 is a diagram illustrating another embodiment of a semiconductor structure that incorporates a contact sidewall spacer with a self-aligned airgap;

"FIG. 3 is a flow diagram illustrating embodiments of a method of forming the semiconductor structure of FIG. 1 or of FIG. 2;

"FIG. 4 is a diagram illustrating a partially completed semiconductor structure formed according to the method of FIG. 3;

"FIG. 5 is a diagram illustrating a partially completed semiconductor structure formed according to the method of FIG. 3;

"FIG. 6 is a flow diagram illustrating an exemplary technique for performing the processes 308-310 of FIG. 3 in order to form the semiconductor structure of FIG. 1;

"FIG. 7 is a diagram illustrating a partially completed semiconductor structure formed using the technique of FIG. 6;

"FIG. 8 is a diagram illustrating a partially completed semiconductor structure formed using the technique of FIG. 6;

"FIG. 9 is a diagram illustrating a partially completed semiconductor structure formed using the technique of FIG. 6;

"FIG. 10 is a diagram illustrating a partially completed semiconductor structure formed using the technique of FIG. 6;

"FIG. 11 is a diagram illustrating a partially completed semiconductor structure formed using the technique of FIG. 6;

"FIG. 12 is a diagram illustrating a partially completed semiconductor structure formed using the technique of FIG. 6;

"FIG. 13 is a diagram illustrating a partially completed semiconductor structure formed using the technique of FIG. 6;

"FIG. 14 is a diagram illustrating a partially completed semiconductor structure formed using the technique of FIG. 6;

"FIG. 15 is a flow diagram illustrating an exemplary technique for performing the processes 308-310 of FIG. 3 in order to form the semiconductor structure of FIG. 2;

"FIG. 16 is a diagram illustrating a partially completed semiconductor structure formed using the technique of FIG. 15;

"FIG. 17 is a diagram illustrating a partially completed semiconductor structure formed using the technique of FIG. 15;

"FIG. 18 is a diagram illustrating a partially completed semiconductor structure formed using the technique of FIG. 15;

"FIG. 19 is a diagram illustrating a partially completed semiconductor structure formed using the technique of FIG. 15; and

"FIG. 20 is a diagram illustrating a partially completed semiconductor structure formed using the technique of FIG. 15."

For additional information on this patent application, see: Chen, Fen; Gambino, Jeffrey P.; He, Zhong-Xiang; Wang, Xin; Wang, Yanfeng. Semiconductor Structure Incorporating a Contact Sidewall Spacer with a Self-Aligned Airgap and a Method of Forming the Semiconductor Structure. Filed October 31, 2012 and posted May 8, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=5938&p=119&f=G&l=50&d=PG01&S1=20140501.PD.&OS=PD/20140501&RS=PD/20140501

Keywords for this news article include: Electronics, Semiconductor, International Business Machines Corporation.

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Source: Electronics Newsweekly