The patent's assignee is
News editors obtained the following quote from the background information supplied by the inventors: "Various embodiments of the present invention relate generally to semiconductor devices, and more specifically, to a semiconductor device including an ESD protection device.
"Electrostatic discharge (ESD) is caused by a discharge of an excess or deficiency of electrons on one surface with respect to another surface or to ground. When a static charge exists on an object, electrons become electrically imbalanced. ESD occurs when the imbalanced electrons attempt to reach equilibrium by traveling to another object having a different voltage potential via a discharge path. However, an electrostatic field corresponding to the discharge path can permanently damage ESD-sensitive devices, such as a field effect transistor (FET) or other semiconductor device.
"Semiconductor devices may include an ESD protection device, such as a buried ESD diode structure disposed under a buried insulator of a semiconductor-on-insulator substrate to protect the semiconductor device from ESD. Deep contacts are required to connect the anode and cathode of the buried ESD diode. When a high-voltage event caused by ESD occurs, the buried ESD diode may shunt current below the buried insulator, which effectively protects the semiconductor device from ESD damage. Further, an increase in thermal dissipation of the heat caused by the ESD may be realized by burying the ESD diode below the buried insulator.
"Recent trends in technology have encouraged a reduction in the size of semiconductor devices. As stated above, however, the conventional buried ESD diode requires deep contacts to connect the anode and cathode. Consequently, a reduction in size of a semiconductor device including a conventional ESD diode is limited by the deep contacts."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "According to at least one embodiment, a semiconductor device comprises a semiconductor-on-insulator (SOI) substrate including a bulk substrate layer, an active semiconductor layer and a buried insulator layer disposed between the bulk substrate layer and the active semiconductor layer. A trench is formed through the SOI substrate to expose the bulk substrate layer. A doped well is formed in the bulk substrate layer adjacent the trench. The semiconductor device further includes at least one doped region different from the doped well formed in the trench.
"According to another embodiment, an electrostatic discharge (ESD) protection device comprises a doped well formed in a bulk substrate layer of a semiconductor-on-insulator (SOI) substrate. A first doped region is formed in a trench of the SOI substrate. The ESD protection device further includes a second doped region different from the first doped region. The second doped region is formed vertically in the trench of the SOI substrate with respect to the first doped region.
"In yet another embodiment, a method of fabricating a semiconductor device comprises forming a trench through a semiconductor-on-insulator (SOI) substrate to expose a bulk substrate layer. The SOI substrate includes the bulk substrate layer, an active semiconductor layer and a buried insulator layer. The buried insulator is disposed between the bulk substrate layer and the active semiconductor layer. The method further includes forming a doped well in the bulk substrate layer adjacent the trench, and forming at least one doped region in the trench to contact the doped well. The at least one doped region is different from the doped well.
"In still another embodiment, a method of fabricating an electrostatic discharge (ESD) protection device comprises forming a doped well in a bulk substrate layer of a semiconductor-on-insulator (SOI) substrate. The method further includes forming a first doped region in a trench of the SOI substrate and a second doped region in the trench of the SOI substrate. The second doped region is different from the first doped region and is formed vertically with respect to the first doped region.
"Additional features and utilities are realized through the various embodiments. Other embodiments and features are described in detail herein and are considered a part of the disclosed embodiments. For a better understanding of the features of the various embodiments, refer to the description and to the drawings.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
"The subject matter described herein is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features are apparent from the following detailed description taken in conjunction with the accompanying drawings. FIGS. 1-13 are a series of views illustrating a method of forming a semiconductor device according to the various embodiments, in which:
"FIG. 1 illustrates a cross-sectional view of a semiconductor-on-insulator (SOI) starting substrate;
"FIG. 2 illustrates formation of a first mask layer on an active semiconductor layer of the SOI substrate shown in FIG. 1;
"FIG. 3 illustrates the SOI substrate of FIG. 2 following an etching process to form a trench that exposes a bulk substrate layer;
"FIG. 4 illustrates formation of a spacer layer on the first mask layer and in the trench of the SOI substrate shown in FIG. 3;
"FIG. 5 illustrates the SOI substrate illustrated in FIG. 4 following etching of the spacer layer to form spacers on sidewalls of the trench;
"FIG. 6 illustrates deposition of ions in the exposed bulk substrate layer of the SOI substrate shown in FIG. 5;
"FIG. 7 illustrates formation of a doped well following the deposition of ions in the exposed bulk substrate of the SOI substrate shown in FIG. 6;
"FIG. 8 illustrates formation of a first doped region in the trench of the SOI substrate illustrated in FIG. 7;
"FIG. 9 illustrates the SOI substrate shown in FIG. 8 after filing the trench with a field oxide material;
"FIG. 10 illustrates the SOI substrate shown in FIG. 9 having a mask partially formed on the spacer layer and the field oxide material;
"FIG. 11 illustrates formation of a cavity following etching of an exposed portion of the field oxide layer of the SOI substrate shown in FIG. 10;
"FIG. 12 illustrates the SOI substrate shown in FIG. 11 after removing the mask and forming a second doped region in the cavity; and
"FIG. 13 illustrates formation of conductive terminals in the first and second doped regions of the SOI substrate shown in FIG. 12.
"FIG. 14 is a flow diagram illustrating a method of fabricating a semiconductor device including an ESD protective device; and
"FIG. 15 is a flow diagram illustrating a method of fabricating an ESD protective device."
For additional information on this patent application, see: Yamashita,
Keywords for this news article include: Electronics, Semiconductor,
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