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Researchers Submit Patent Application, "Power Device Structures and Methods", for Approval

May 21, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Zeng, Jun (Torrance, CA); Darwish, Mohamed N. (Campbell, CA), filed on October 25, 2012, was made available online on May 8, 2014.

No assignee for this patent application has been made.

News editors obtained the following quote from the background information supplied by the inventors: "The present application relates to power semiconductor devices, methods, and circuits, and more particularly to power semiconductor devices, methods, and circuits which make use of permanent or immobile electrostatic charge.

"Note that the points discussed below may reflect the hindsight gained from the disclosed inventions, and are not necessarily admitted to be prior art.

"Power MOSFETs are widely used as switching devices in many electronic applications. In order to minimize the conduction power loss it is desirable that power MOSFETs have a low specific on-resistance (R.sub.SP or R*A), which is defined as the product of the on-resistance of the MOSFET multiplied by the active die area. In general, the on-resistance of a power MOSFET is dominated by the channel resistance and the drift region resistances which include the channel resistance, spreading resistance and the epitaxial layer resistance. Recently, the so called superjunction structure has been developed to reduce the drift region resistance. The superjunction is constructed by paralleling highly doped alternating p-type and n-type layers or pillars. The doping concentrations of n-type pillar (the n-type drift region), for the same breakdown voltage, can be significantly higher than that of conventional drift region provided that the total charge of n-type pillar is designed to be balanced with charge in the p-type pillar. In order to fully realize the merit of the superjunction, it is desirable to pack many pillars in a given area to achieve a lower R.sub.SP. However, the minimum widths, which can be reached in device manufacturing, of the n-type and p-type pillars set a limitation on the cell pitch that can be achieved and the resulting device size.

"With reference to FIG. 1, a cross-sectional structural diagram depicts a power MOSFET design as shown in other patent applications which are commonly owned. (See the list of applications given below, which all have at least overlapping ownership, inventorship and copendency with the present application, and all of which are hereby incorporated by reference.) Note that these applications are not necessarily prior art to the present application. This device includes a drain region 102, e.g. a substrate, underlying a p-type drift region 104, which may be provided by an epitaxial layer. A p-body region 106 (contacted by a p+ body contact region 110) separates a source region 108 from the drift region 104. A trench is largely filled with dielectric material 114, but also contains a gate electrode 112. Gate electrode 112 is capacitively coupled to nearby portions of body 106, so that, depending on the applied gate voltage, an inversion layer may be formed at the surface of the body region 106, creating a channel. Frontside source metallization 101 makes ohmic contact to source and body, and backside drain metallization 103 makes ohmic contact to the drain diffusion 102.

"Another very important feature is that the device incorporates a sheet of fixed or permanent positive charge (Q.sub.F) 116, at or near the sidewalls of the trench, which balances the charge of p-type in the off state. The permanent charge 116 also forms a electron drift region in a power MOSFET by forming an inversion layer along the interface between the dielectric material 114 (e.g. oxide) and P Epi layer 104. By making use of this new concept, the scaling limitation due to inter-diffusion of p-type pillar and n-type pillar can be reduced. Consequently, a small cell pitch and high pillar packing density can be realized to reduce the device total on-resistance and R.sub.SP.

"However, as the cell pitch is reduced the intrinsic capacitances of the device, such as gate-to-source capacitance (C.sub.gs) and gate-to-drain capacitance (C.sub.gd), also increase. As a consequence, the switching loss of the device increases. This is undesirable.

"The turn-on characteristics of the device in FIG. 1 have been simulated. The key components of device capacitances during the device turn-on process are illustrated by the internal electric field lines shown in FIG. 2. The most significant component which controls the device switching, power losses, is the total charge associated with charging or discharging the gate-drain capacitance C.sub.gd. This charge is the so-called 'Miller charge' Q.sub.gd. Therefore, it is important to reduce Q.sub.gd in order to reduce total losses."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "The present inventors have realized that the Miller charge of a structure like that of FIG. 1 can be reduced in a very simple way. As shown in FIG. 2, coupling from the bottom of the gate electrode to the permanent charge along the lower sidewalls of the trench is an important contributor to the Miller capacitance. The present application teaches that a conductive shield layer should be positioned to reduce this coupling, and thus reduce the gate-to-drain capacitance.

"The disclosed innovations, in various embodiments, provide one or more of at least the following advantages. However, not all of these advantages result from every one of the innovations disclosed, and this list of advantages does not limit the various claimed inventions. Reduced Miller charge; Reduced gate-drain capacitances; Improved R.sub.sp (specific on-resistance); Improved device switching speed; Reduced ratio of C.sub.GD to C.sub.GS capacitances. (This reduces common-mode conduction.)

BRIEF DESCRIPTION OF THE DRAWINGS

"The disclosed inventions will be described with reference to the accompanying drawings, which show important sample embodiments and which are incorporated in the specification hereof by reference, wherein:

"FIG. 1 is a cross-sectional structural diagram depicting a power device according to previous applications of the same assignee;

"FIG. 2 depicts electric field vectors in a device during turn-on;

"FIG. 3(a) is a cross-sectional structural diagram depicting a power device in accordance with one illustrative class of embodiments;

"FIG. 3(b) is a cross-sectional structural diagram depicting a power device in accordance with yet another illustrative class of embodiments;

"FIG. 4(a) is a cross-sectional structural diagram depicting a power device in accordance with yet another illustrative class of embodiments;

"FIG. 4(b) is a cross-sectional structural diagram depicting a power device in accordance with yet another illustrative class of embodiments;

"FIG. 5(a) is a cross-sectional structural diagram depicting a power device in accordance with yet another illustrative class of embodiments;

"FIG. 5(b) is a cross-sectional structural diagram depicting a power device in accordance with yet another illustrative class of embodiments;

"FIG. 5 is a cross-sectional structural diagram depicting a power device in accordance with yet another illustrative class of embodiments;

"FIG. 5(d) is a cross-sectional structural diagram depicting a power device in accordance with yet another illustrative class of embodiments;

"FIG. 6(a) is a cross-sectional structural diagram depicting a power device in accordance with yet another illustrative class of embodiments;

"FIG. 6(b) is a cross-sectional structural diagram depicting a power device in accordance with yet another illustrative class of embodiments;

"FIG. 7 is a graph plotting gate voltage against gate charge;

"FIG. 8 is a cross-sectional structural diagram depicting a conventional quasi-planar power device;

"FIG. 9(a) is a cross-sectional structural diagram depicting a power device in accordance with an illustrative class of embodiments;

"FIG. 9(b) is a cross-sectional structural diagram depicting a power device in accordance with yet another illustrative class of embodiments;

"FIG. 9 is a cross-sectional structural diagram depicting a power device in accordance with yet another illustrative class of embodiments;

"FIG. 9(d) is a cross-sectional structural diagram depicting a power device in accordance with yet another illustrative class of embodiments;

"FIG. 10(a) is a cross-sectional structural diagram depicting a power device in accordance with yet another illustrative class of embodiments;

"FIG. 10(b) is a cross-sectional structural diagram depicting a power device in accordance with yet another illustrative class of embodiments;

"FIG. 10 is a cross-sectional structural diagram depicting a power device in accordance with yet another illustrative class of embodiments;

"FIG. 10(d) is a cross-sectional structural diagram depicting a power device in accordance with yet another illustrative class of embodiments;

"FIG. 11(a) is a cross-sectional structural diagram depicting a power device in accordance with yet another illustrative class of embodiments;

"FIG. 11(b) is a cross-sectional structural diagram depicting a power device in accordance with yet another illustrative class of embodiments;

"FIG. 11 is a cross-sectional structural diagram depicting a power device in accordance with yet another illustrative class of embodiments;

"FIG. 11(d) is a cross-sectional structural diagram depicting a power device in accordance with yet another illustrative class of embodiments;

"FIG. 12(a) is a cross-sectional structural diagram depicting a power device in accordance with yet another illustrative class of embodiments;

"FIG. 12(b) is a cross-sectional structural diagram depicting a power device in accordance with yet another illustrative class of embodiments;

"FIG. 13 is a graph plotting gate voltage against gate charge;

"FIG. 14 is a cross-sectional structural diagram depicting a edge termination structure, in accordance with an illustrative class of embodiments;

"FIGS. 15(a)-15(b) show blocking characteristics, for the termination structure of FIG. 14, at the onset of breakdown, for two different fixed charge densities;

"FIG. 16 is a cross-sectional structural diagram depicting a edge termination structure, in accordance with another illustrative class of embodiments; and

"FIGS. 17(a)-17(b) show blocking characteristics, for the termination structure of FIG. 16, at the onset of breakdown, for two different fixed charge densities."

For additional information on this patent application, see: Zeng, Jun; Darwish, Mohamed N. Power Device Structures and Methods. Filed October 25, 2012 and posted May 8, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=5917&p=119&f=G&l=50&d=PG01&S1=20140501.PD.&OS=PD/20140501&RS=PD/20140501

Keywords for this news article include: Patents, Electronics, Semiconductor.

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Source: Electronics Newsweekly