News Column

Researchers Submit Patent Application, "Package Substrate and Chip Package Using the Same", for Approval

May 21, 2014

By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Lin, Po-Chun (Changhua County, TW); Pei, Han-Ning (Taipei City, TW), filed on October 25, 2012, was made available online on May 8, 2014.

No assignee for this patent application has been made.

News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates to semiconductor devices. More particularly, the present invention relates to a package substrate and a chip package structure.

"In the integrated circuit (IC) packaging industry, there is a continuous desire to provide higher and higher density IC packages for semiconductor die having increasing numbers of input/output (I/O) terminal pads. When using a conventional wire bonding packaging technique, the pitch, or spacing between adjacent bonding wires becomes finer and finer as the number of I/O terminal pads increases for a given size die.

"As known in the art, semiconductor die is typically sealed within a package of moldable material to protect it from environmental stresses. The moldable material is fed into cavities of a mold, thus flowing over the semiconductor die. The moldable material is then hardened to encapsulate the semiconductor die. However, the moldable material may bleed onto the solder mask. The mold bleed can adversely affect bonding of the external contacts to the bonding sites. The mold bleed can also adversely affect the electrical connections to the external contacts, and the cosmetic appearance of the package. Additionally, a subsequent process may be necessary to remove the mold bleed from the substrate surface and the equipment."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "In one aspect, the present invention provides a package substrate including a base layer and a dam structure or a dent structure on at least one side of the base layer. The base layer may be a CCL core, a molding compound, or an epoxy base.

"In another aspect, the present invention provides a package substrate including a base layer having a first side and a second side that is opposite to the first side; a first solder mask on a first side of the base layer; and a second solder mask on a second side of the base layer, wherein at least one of the first and second solder masks has thereon a dam structure and a dent structure.

"In accordance with another aspect of the invention, a chip package includes a package substrate having a chip mounting side and a bottom side that is opposite to the chip mounting side; a semiconductor chip mounted on the chip mounting side; and a dam structure and a dent structure on the bottom side of the package substrate.

"These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.


"FIG. 1 is schematic, cross-sectional diagram showing a germane portion of a package substrate in accordance with one embodiment of this invention.

"FIG. 2 is a schematic, cross-sectional view of a window BGA package for DRAM chips in accordance with another embodiment of this invention."

For additional information on this patent application, see: Lin, Po-Chun; Pei, Han-Ning. Package Substrate and Chip Package Using the Same. Filed October 25, 2012 and posted May 8, 2014. Patent URL:

Keywords for this news article include: Patents, Electronics, Semiconductor.

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Source: Electronics Newsweekly

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