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Researchers Submit Patent Application, "Multigate Field Effect Transistor and Process Thereof", for Approval

May 21, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Liu, Chih-Chien (Taipei City, TW); Wu, Chun-Yuan (Yun-Lin County, TW); Lin, Chin-Fu (Tainan City, TW); Chien, Chin-Cheng (Tainan City, TW); Hsu, Chia-Lin (Tainan City, TW), filed on October 29, 2012, was made available online on May 8, 2014.

The patent's assignee is United Microelectronics Corp.

News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates generally to a multigate field effect transistor and a process thereof, and more specifically to a multigate field effect transistor and a process thereof that forms voids in a dielectric layer between fin-shaped structures.

"With increasing miniaturization of semiconductor devices, various multi-gate MOSFET devices have been developed. The multi-gate MOSFET is advantageous for the following reasons. First, manufacturing processes of multi-gate MOSFET devices can be integrated into traditional logic device processes, and thus are more compatible. In addition, since the three-dimensional structure of the multi-gate MOSFET increases the overlapped area between the gate and the substrate, the channel region is controlled more effectively. This therefore reduces drain-induced barrier lowering (DIBL) effect and short channel effect. Moreover, the channel region is longer for the same gate length. Therefore, the current between the source and the drain is increased.

"A multigate field effect transistor component includes fin-shaped structures on a substrate, and a gate structure and a source/drain on each of the fin-shaped structures, to form multigate field effect transistors having multi gate channels. However, assizes of multigate field effect transistors shrink, the parasitic capacitances between each of the fin-shaped structures become large and degrade electrical performances of the multigate field effect transistors."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "The present invention provides a multigate field effect transistor and a process thereof, which forms voids in a dielectric layer between two fin-shaped structures, so that the parasitic capacitances of the multigate field effect transistor can be reduced, and the aforesaid problem can therefore be solved.

"The present invention provides a multigate field effect transistor including two fin-shaped structures and a dielectric layer. The two fin-shaped structures are located on a substrate. The dielectric layer covers the substrate and the two fin-shaped structures, and at least two voids are located in the dielectric layer between the two fin-shaped structures.

"The present invention provides a multigate field effect transistor process including the following steps. Two fin-shaped structures are formed on a substrate. A dielectric layer is formed to cover the substrate and the two fin-shaped structures, wherein at least two voids are formed in the dielectric layer between the two fin-shaped structures.

"According to the above, the present invention provides a multigate field effect transistor and a process thereof, which forms voids in a dielectric layer between two fin-shaped structures, so that the parasitic capacitances of the multigate field effect transistor, especially between the fin-shaped structures, can be reduced. Moreover, processes for forming a dielectric layer with voids in the dielectric layer between the fin-shaped structures in the present invention can reduce processing costs compared to processes intended to fully fill the dielectric layer (with no voids).

"These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIGS. 1-7 schematically depict cross-sectional views of a multigate field effect transistor process according to a first embodiment of the present invention.

"FIGS. 8-9 schematically depict cross-sectional views of a multigate field effect transistor process according to a second embodiment of the present invention.

"FIG. 10 schematically depicts a top view of a multigate field effect transistor according to an embodiment of the present invention.

"FIG. 11 schematically depicts a cross-sectional view of a multigate field effect transistor process according to an embodiment of the present invention."

For additional information on this patent application, see: Liu, Chih-Chien; Wu, Chun-Yuan; Lin, Chin-Fu; Chien, Chin-Cheng; Hsu, Chia-Lin. Multigate Field Effect Transistor and Process Thereof. Filed October 29, 2012 and posted May 8, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=5903&p=119&f=G&l=50&d=PG01&S1=20140501.PD.&OS=PD/20140501&RS=PD/20140501

Keywords for this news article include: United Microelectronics Corp.

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Source: Electronics Newsweekly


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