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Researchers Submit Patent Application, "Display Apparatus, Driving Module Thereof, Voltage Control Circuit and Voltage Control Method", for Approval

May 21, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors CHAN, Pin-Yu (Hsin-Chu, TW); HSU, Chih-Che (Hsin-Chu, TW); CHEN, Yung-Chih (Hsin-Chu, TW); TSAI, Ming-Yen (Hsin-Chu, TW), filed on July 9, 2013, was made available online on May 8, 2014.

No assignee for this patent application has been made.

News editors obtained the following quote from the background information supplied by the inventors: "FIG. 1 is a block view of a conventional liquid crystal display apparatus. As shown, the conventional liquid crystal display apparatus 100 includes a glass substrate 102 and a printed circuit board 104; wherein the printed circuit board 104 is coupled to the glass substrate 102 via a flexible substrate 106.

"The glass substrate 102 has a display area 112 and two gate driver on arrays (GOAs) 114 and 116. The display area 112 includes a plurality of gate lines 118 and a plurality of source lines 120, which are arranged to each other in a sequential and intersectional manner. A liquid crystal unit 122, served as a pixel cell, is disposed at each intersectional point of the gate lines 118 and the source lines 120; and accordingly the liquid crystal units 122 are arranged in a matrix manner. In addition, each liquid crystal unit 122 is coupled to the corresponding gate line 118 and source line 120 via a thin film transistor 124.

"The gate driver on arrays 114 and 116 are coupled to the display area 112 via the gate lines 118 and configured to generate a plurality of scanning signals (not shown) according to an operating voltage. The scanning signals are transmitted to the gate lines 118 and thereby turning on the thin film transistors 124 coupled to the gate lines 118. However, when the liquid crystal display apparatus 100 is operated in a relatively-low temperature, the output currents of the thin film transistors 124 may drop substantially and consequently the liquid crystal display apparatus 100 may not be able to display images normally.

"Specifically, the aforementioned issue is getting more serious if the gate driver on arrays 114 and 116 are directly manufactured on the glass substrate 102 by the GOA technical rather than employing an external integrated driving circuit.

"In order to solve the above issue, conventionally the printed circuit board 104 is disposed with a temperature sensor 130 thereon. Thus, The gate driver on arrays 114 and 116 can have the potential levels of the operating voltages thereof raised up if the temperature sensor 130 senses that the environmental temperature is lower than a threshold degree, and consequentially the liquid crystal display apparatus 100 still can display images normally in a relatively-low temperature."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "The present disclosure provides voltage control circuit and voltage control method for compensating the operating voltage of the gate driver array of the display apparatus. Thus, the display apparatus can display images normally in different temperatures.

"The present disclosure further provides a driving module of a display apparatus. The driving module is capable of driving the display apparatus to display images normally in different temperatures.

"The present disclosure still provides a display apparatus capable of displaying images normally in different temperatures.

"An embodiment of the disclosure provides a voltage control circuit adapted to be used to control a first clock signal received by a gate driver array of a display apparatus. The voltage control circuit includes a gate trigger pulse generator unit and a controller. The gate trigger pulse generator unit is configured to receive a reference voltage and one of a plurality of driving signals outputted from the gate driver array and accordingly generate a gate trigger pulse, wherein a pulse width of the gate trigger pulse is controlled by the gate trigger pulse generator unit according to a potential-level relationship between the received driving signal and the reference voltage. The controller, coupled to the gate trigger pulse generator unit, is configured to receive the gate trigger pulse and control a potential difference of a pulse level of the first clock signal according to the pulse width of the gate trigger pulse.

"Another embodiment of the disclosure provides a driving module of a display apparatus. The display apparatus includes a plurality of pixel rows arranged in a sequence and each pixel row includes a plurality of pixels. The driving module includes a gate driver array, a voltage control circuit and an operating voltage generator circuit. The gate driver array is coupled to the pixel rows and configured to receive a first clock signal and output a plurality of driving signals in a sequence to drive the pixel rows, respectively. The voltage control circuit is coupled to the gate driver array and configured to control a potential difference of a pulse level of the first clock signal. The voltage control circuit includes a gate trigger pulse generator unit and a controller. The gate trigger pulse generator unit is configured to receive a reference voltage and one of a plurality of driving signals outputted from the gate driver array and accordingly generate a gate trigger pulse, wherein a pulse width of the gate trigger pulse is controlled by the gate trigger pulse generator unit according to a potential-level relationship between the received driving signal and the reference voltage. The controller is coupled to the gate trigger pulse generator unit and configured to receive the gate trigger pulse and output a control voltage according to the pulse width of the gate trigger pulse thereby controlling the potential difference of a pulse level of the first clock signal. The operating voltage generator circuit is coupled to the gate driver array and configured to provide the first clock signal and adjust the first clock signal according to the control signal.

"Still another embodiment of the disclosure provides a display apparatus, which includes a substrate, a plurality of gate lines, a gate driver array, an operating voltage generator circuit and a voltage control circuit. The substrate includes a display area. The display area includes a plurality of pixel rows arranged in a sequence. Each pixel row includes a plurality of pixels. The gate lines are respectively coupled to the pixels of the respective pixel rows. The gate driver array is configured to receive a first clock signal. The gate driver array includes a plurality of series-coupled driving shift registers and at least one dummy shift register. The series-coupled driving shift registers are coupled to the gate lines respectively and configured to sequentially output a first driving signal to the respective gate lines according to the first clock signal and thereby turning on the pixels coupled to the gate lines. The dummy shift register is coupled to the last-stage driving shift register of the driving shift registers and configured to receive the first driving signal from the last-stage driving shift register and generate a second driving signal. The operating voltage generator circuit is coupled to the gate driver array and configured to provide the first clock signal. The voltage control circuit, coupled to the dummy shift register and the operating voltage generator circuit, is configured to control a potential difference of a pulse level of the first clock signal according to a potential-level relationship between a reference voltage and either one of the first driving signals or one of the second driving signals.

"Yet another embodiment of the disclosure provides a voltage control method adapted to be used to control a first clock signal of a gate driver array of a display apparatus. The voltage control method includes steps of: receiving a driving signal outputted from the gate driver array and generating a gate trigger pulse according to the received driving signal; controlling a pulse width of the gate trigger pulse according to a potential-level relationship between the driving signal and a reference voltage; and controlling a potential difference of a pulse level of the first clock signal according to the pulse width of the gate trigger pulse.

"In summary, by monitoring the driving signals outputted from the gate driver array of the display apparatus, the present invention can dynamically adjust the potential difference of the pulse level of the first clock signal in time. In addition, by directly disposing the voltage control circuit on either the glass substrate or the printed circuit board, the present invention can have lower hardware cost.

BRIEF DESCRIPTION OF THE DRAWINGS

"The present disclosure will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:

"FIG. 1 is a block view of a conventional liquid crystal display apparatus;

"FIG. 2A is a block view of a display apparatus in accordance with an embodiment of the present disclosure;

"FIG. 2B is a schematic waveform view of the potential difference between the logic-high and logic-low voltage levels of the first clock signal VCK;

"FIG. 3A is a block view of the gate driver array shown in FIGS. 2 and 9 in accordance with an embodiment of the present disclosure;

"FIG. 3B is an alternative block view of the gate driver array shown in FIGS. 2 and 9 in accordance with another embodiment of the present disclosure;

"FIG. 4 is a schematic circuit view of the shift register shown in FIG. 3B;

"FIG. 5 is a schematic timing sequence diagram of the signals associated with the driving shift register shown in FIG. 4;

"FIG. 6 is a schematic block view of the voltage control circuit shown in FIGS. 2A and 8;

"FIG. 7 is a schematic waveform diagram of the signals associated with the voltage control circuit shown in FIG. 6;

"FIG. 8 is a schematic timing sequence diagram of the signals associated with the voltage control circuit shown in FIG. 6;

"FIG. 9 is a block view of a display apparatus in accordance with another embodiment of the present disclosure; and

"FIGS. 10A and 10B are flowcharts illustrating a voltage control method in accordance with an embodiment of the present disclosure."

For additional information on this patent application, see: CHAN, Pin-Yu; HSU, Chih-Che; CHEN, Yung-Chih; TSAI, Ming-Yen. Display Apparatus, Driving Module Thereof, Voltage Control Circuit and Voltage Control Method. Filed July 9, 2013 and posted May 8, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=5035&p=101&f=G&l=50&d=PG01&S1=20140501.PD.&OS=PD/20140501&RS=PD/20140501

Keywords for this news article include: Patents, Electronics, Circuit Board.

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Source: Electronics Newsweekly


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