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Researchers Submit Patent Application, "Compact Model for Device/Circuit/Chip Leakage Current (Iddq) Calculation Including Process Induced Uplift...

May 21, 2014



Researchers Submit Patent Application, "Compact Model for Device/Circuit/Chip Leakage Current (Iddq) Calculation Including Process Induced Uplift Factors", for Approval

By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Chang, Paul (Mahopac, NY); Deng, Jie (Poughkeepsie, NY); Hook, Terrence B. (Jericho, VT); Loo, Sim Y. (Rochester, MN); Mocuta, Anda C. (LaGrangeville, NY); Park, Jeae-Eun (Wappingers Falls, NY); Rim, Kern (Yorktown Heights, NY); Yu, Xiaojun (Sunnyvale, CA), filed on January 6, 2014, was made available online on May 8, 2014.

The patent's assignee is International Business Machines Corporation.

News editors obtained the following quote from the background information supplied by the inventors: "Leakage assessment has become very crucial part of circuit design, both in portable low-power applications where leakage current can limit the interval between battery recharges, and also high-power applications where the leakage current can be a substantial portion of the total power dissipation of the operating unit. Current look-up table and general-purpose circuit simulation program (e.g., SPICE) model approaches offer limited benefit at best and the scope of coverage is very limited as well. For example, current SPICE models and circuit simulation programs are not generally focused on calculating quiescent current (often called IDDQ).

"It would be highly desirable to provide an improved solution for circuit simulators to implement IDDQ leakage-specific models into the current design flows.

"Furthermore, it is desirable to provide an improved solution for circuit simulators to implement IDDQ leakage specific models into the current design flows wherein the leakage model covers all geometries with wide temperature and voltage ranges without tedious stacking factor calculations nor spread sheet based IDDQ calculation.

"Further more, in such a solution, it is desirable to provide an improved solution for circuit simulators to implement leakage specific models into the current design flows wherein the leakage model allows all parasitic and proximity effects to be incorporated for IDDQ calculation."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "There is provided a system and method for circuit simulators (e.g., SPICE) to model the IDDQ quiescent current state when conducting performance analysis of integrated circuit designs, and particularly, implementing leakage specific models into the design flows wherein the leakage model covers all geometries with wide temperature and voltage ranges without tedious stacking factor calculations nor spread sheet based Iddq calculation. The leakage model further allows all parasitic and proximity effects to be incorporated into the design flow for Iddq calculation.

"Since they can be compiled and operated using a netlist of interest for the performance analysis, the leakage specific models implemented into the design flows provides a novel solution for leakage assessment.

"More particularly, there is provided a system and method for simulating an integrated circuit (IC) design in a circuit design simulator, the method comprising: receiving data representing a circuit design, the data configured for input to and processing by the circuit design simulator, the data specifying an uplift switch value for an integrated circuit quiescent current (IDDQ) prediction macro, the switch value corresponding to one of: the device, cell, circuit, or IC chip level of design being simulated; when simulating the circuit, using the IDDQ prediction macro to model a leakage current prediction for the circuit design, the leakage current prediction determinable at a device, cell, circuit, or IC chip level of the design, automatically calculating one or more uplift factors representing device variation effects for use in the leakage current prediction model according to the switch value, an uplift factor being a function of a statistical quantity .sigma..sub.lpoly of the polysilicon gate length variation of a transistor, a statistical quantity .sigma..sub.vtsat of the transistor saturation threshold voltage variation, and a statistical quantity .sigma..sub.subx of the transistor sub threshold slope, wherein for a specified uplift factor switch value, .sigma..sub.lpoly=.sigma..sub.ACLV; .sigma..sub.vtsat is calculated as a function of a statistical quantity .sigma..sub.VthRDF defining a 1-sigma Random-Dopant-Fluctuation Induced Vth Variation, and .sigma..sub.subx is calculated as a function of a statistical quantity .sigma..sub.subVth defining a 1-sigma subVth Slope Variation, where Vth is the threshold voltage of the transistor device, and .sigma..sub.ACLV is a 1-sigma Across-Chip Lpoly Length Variation value due to within chip Across-Chip-Length-Variation, wherein a processor device performs at least one of the receiving, using, modeling and uplift factor calculating.

"Further to this embodiment, the statistical modeling includes obtaining data used to predict current leakage resulting from proximity effects inherent in the circuit design.

"Further to this embodiment, the statistical modeling includes obtaining data used to predict current leakage as a function of device variations effects, the uplift factor calculated based on the device variations effects.

"According to a further aspect, there is provided a system for simulating current leakage of a semiconductor device design comprising: a memory; a processor in communications with the memory, wherein the computer system is capable of performing a method comprising: receiving data representing a circuit design, the data configured for input to and processing by the circuit design simulator, the data specifying an uplift switch value for an integrated circuit quiescent current (IDDQ) prediction macro, the switch value corresponding to one of: the device, cell, circuit, or IC chip level of design being simulated; when simulating the circuit, using the IDDQ prediction macro to model a leakage current prediction for the circuit design, the leakage current prediction determinable at a device, cell, circuit, or IC chip level of the design, automatically calculating one or more uplift factors representing device variation effects for use in the leakage current prediction model according to the switch value, an uplift factor being a function of a statistical quantity .sigma..sub.lpoly of the polysilicon gate length variation of a transistor, a statistical quantity .sigma..sub.vtsat of the transistor saturation threshold voltage variation, and a statistical quantity .sigma..sub.subx of the transistor sub-threshold slope, wherein for a specified uplift factor switch value, .sigma..sub.lpoly=.sigma..sub.ACLV; .sigma..sub.vtsat is calculated as a function of a statistical quantity .sigma..sub.VthRDF defining a 1-sigma Random-Dopant-Fluctuation Induced Vth Variation, and .sigma..sub.subx is calculated as a function of a statistical quantity .sigma..sub.subVth defining a 1-sigma subVth Slope Variation, where Vth is the threshold voltage of the transistor device, and .sigma..sub.ACLV is a 1-sigma Across-Chip Lpoly Length Variation value due to within chip Across-Chip-Length-Variation, wherein a processor device performs at least one of the receiving, using, modeling and uplift factor calculating.

"Moreover, the invention provides a computer program product having instructions for simulating current leakage of a semiconductor device design.

"Advantageously, the system and method of the invention implements leakage specific models into the design flows for 45 nm node technologies and beyond.

BRIEF DESCRIPTION OF THE DRAWINGS

"The objects, features and advantages of the present invention will become apparent to one of ordinary skill in the art, in view of the following detailed description taken in combination with the attached drawings, in which:

"FIG. 1 illustrates a general schematic of the IDDQ model methodology 10 according to an embodiment of the invention. In the IDDQ method, parameters are given that include at least

"FIG. 2 illustrates a device variation modeling approach 50 used in the determining of uplift factor(s) for the IDDQ model methodology;

"FIG. 3 illustrates a formula equation 80 that summarizes computation of IDDQ uplift and corners factors and particularly how a total variation, .sigma..sub.tot, includes a sum of various components at the device/circuit/chip level;

"FIG. 4 illustrates how a particular Iddq Uplift switch 110 is implemented in the IDDQ leakage model of the present invention for providing the uplift factors;

"FIG. 5 illustrates an example IDDQ SPICE Model Topology and Working Flow 150 according to one embodiment;

"FIGS. 6A and 6B depict an implementation of the IDDQ modeling method that can be called from a simulator program for precise current leakage assessment of a device/circuit/chip level design; and,

"FIG. 7 shows a computing environment that may be used to carry out the invention."

For additional information on this patent application, see: Chang, Paul; Deng, Jie; Hook, Terrence B.; Loo, Sim Y.; Mocuta, Anda C.; Park, Jeae-Eun; Rim, Kern; Yu, Xiaojun. Compact Model for Device/Circuit/Chip Leakage Current (Iddq) Calculation Including Process Induced Uplift Factors. Filed January 6, 2014 and posted May 8, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=263&p=6&f=G&l=50&d=PG01&S1=20140501.PD.&OS=PD/20140501&RS=PD/20140501

Keywords for this news article include: Electronics, Semiconductor, International Business Machines Corporation.

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Source: Electronics Newsweekly