News Column

Patent Issued for Semiconductor Package Having Electrical Connecting Structures and Fabrication Method

May 21, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Lin, Pang-Chun (Taichung, TW); Li, Chun-Yuan (Taichung, TW); Tang, Fu-Di (Taichung, TW); Huang, Chien-Ping (Taichung, TW); Ke, Chun-Chi (Taichung, TW), filed on February 27, 2013, was published online on May 6, 2014.

The assignee for this patent, patent number 8716861, is Siliconware Precision Industries Co., Ltd. (Taichung, TW).

Reporters obtained the following quote from the background information supplied by the inventors: "The present invention relates generally to package structures and fabrication methods thereof, and more particularly, to a QFN (Quad Flat Non-leaded) semiconductor package having electrical connecting structures and a fabrication method thereof.

"Conventionally, a lead frame is used as a chip carrier for carrying a chip so as to form a semiconductor package. The lead frame essentially comprises a die pad and a plurality of leads formed at the periphery of the die pad. A chip is adhered to the die pad and electrically connected to the leads through a plurality of bonding wires. The chip, the die pad, the bonding wires and inner sections of the leads are then encapsulated by a packaging resin so as to form a semiconductor package having a lead frame.

"Developing high integration and high density package structures has become a goal of semiconductor industries. Carriers for chip scale packages generally comprise lead frames, flexible substrates, rigid substrates and so on. Therein, lead frames are widely used in chip scale packages in electronic products due to their low costs and ease in processing. For example, a QFN (Quad Flat Non-leaded) package is a lead frame based chip scale package, which is characterized in that the leads thereof do not extend out from the package sides, thus reducing the overall package size.

"FIG. 1A is a sectional view of a QFN package using a lead frame as a chip carrier as disclosed by U.S. Pat. Nos. 6,143,981, 6,130,115 and 6,198,171. Referring to FIG. 1A, a chip 12 is disposed on a lead frame 10 and electrically connected to leads 11 of the lead frame 10 through bonding wires 13, and an encapsulant 14 is formed to encasuplate the lead frame 10, the chip 12 and the bonding wires 13, wherein the bottom surfaces of the lead frame 10 and the leads 11 are exposed from the encapsulant 14 for mounting and electrically connecting an external device such as a printed circuit board through a solder material (not shown).

"However, as shown in FIG. 1B, since the exposed surfaces of the leads 11 are flush with the encapsulant 14, when solder balls are mounted on the leads 11 for electrically connecting an external printed circuit board, solder bridge is likely to be formed between adjacent solder balls, thereby resulting in poor electrical connection between the package and the printed circuit board.

"FIGS. 2A to 2D show a method for fabricating a QFN package without a carrier as disclosed by U.S. Pat. No. 5,830,800 and No. 6,498,099.

"As shown in FIG. 2A, a plurality of electroplated projections 21 is formed on a copper plate 20 by electroplating.

"As shown in FIG. 2B, a chip 22 is mounted on the electroplated projections 21 and electrically connected therewith through gold wires 23. Then, an encapsulant 24 is formed on the copper plate 20 to encapsulate the electroplated projections 21, the chip 22 and the gold wires 23.

"As shown in FIGS. 2C and 2D, the copper plate 20 is removed to expose the bottom surfaces of the electroplated projections 21 and the encapsulant 24 such that an antioxidiation coating 25 is applied to the bottom surfaces of the electroplated projections 21 and the encapsulant 24, the antioxidation coating 25 partially exposing the electroplated projections 21. Further, solder balls 26 are mounted on the electroplated projections 21.

"However, as shown in FIG. 2E, due to different CTEs of the antioxidation coating 25 and the encapsulant 24, delamination is easy to occur to the interface between the antioxidation coating 25 and the encapsualnt 24. As such, moisture can easily permeate therebetween and thus causes electrical leakage of the electroplated projections 21, thereby adversely affecting the electrical performance of the package. Further, as shown in FIG. 2C, since the surfaces of the electroplated projections 21 are flush with the surface of the encapsulant 24, the surfaces of the electroplated projections 21 can easily be scratched during the fabrication process. Furthermore, a soldering process or thermal cycling in practical applications may cause permeation of solder material into the interface between the antioxidation coating 25 and the encapsulant 24, thus resulting in electrical leakage and even short circuit at the interface.

"In addition, if the electroplated projections 21 are located far away from the chip 22, long gold wires 23 are required, which accordingly increases the fabrication cost.

"Therefore, it is imperative to overcome the above drawbacks of the prior art."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "In view of the above drawbacks of the prior art, the present invention provides a semiconductor package having electrical connecting structures, which comprises: a conductive layer having a die pad and a plurality of traces disposed at the periphery of the die pad, wherein the traces each comprise a trace body, a finger pad formed at one end of the trace body and positioned proximate to the die pad, and a trace end formed at the other end of the trace body and opposite to the finger pad; a chip mounted on the die pad; a plurality of bonding wires electrically connecting the chip and the finger pads; an encapsulant encapsulating the chip and the bonding wires, wherein the encapsulant has a plurality of cavities with a depth greater than a thickness of the die pad and the traces of the conductive layer for embedding the die pad and the traces therein, the cavities allowing the surfaces of the die pad and the traces to be exposed from the encapsulant via the cavities; a solder mask layer formed on the exposed surface of the conductive layer and a bottom surface of the encapsulant and having a plurality of openings formed therein for exposing the trace ends; and a plurality of solder balls formed in the openings of the solder mask layer so as to electrically connect to the trace ends, respectively.

"In the above semiconductor package, the difference between the depth of the cavities and the thickness of the die pad and the traces of the conductive layer can be in the range of from 2 to 30 micrometers. Further, the finger pads can extend towards the die pad so as to reduce the length of the bonding wires, thereby reducing the packaging cost.

"The present invention further provides a fabrication method of a semiconductor package having electrical connecting structures, which comprises: providing a metal board with a plurality of substrate units; forming a patterned metal layer on the substrate units; forming a conductive layer on the metal layer, wherein the conductive layer has a die pad and a plurality of traces disposed at the periphery of the die pad, the traces each comprising a trace body, a finger pad formed at one end of the trace body and positioned proximate to the die pad, and a trace end formed at the other end of the trace body and opposite to the finger pad; mounting a chip on the die pad and electrically connecting the chip to the finger pads through bonding wires; forming an encapsulant to cover the chip, the bonding wires and the conductive layer; removing the metal board and the metal layer so as to expose at least a portion of a surface of the conductive layer, wherein the encapuslant has a plurality of cavities with a depth greater than the thickness of the die pad and the traces of the conductive layer for embedding the die pad and the traces therein; forming a solder mask layer on the exposed at least a portion of the surface of the conductive layer and a bottom surface of the encapsulant, and forming a plurality of openings in the solder mask layer to expose the trace ends; forming a plurality of solder balls in the openings of the solder mask layer, respectively; and singulating the substrate units from each other so as to obtain a plurality of semiconductor packages.

"In the above fabrication method, the metal board can be made of copper; the metal layer can be made of one or more materials selected from the group consisting of Ni, Sn and Pb; and the metal layer can have a thickness between 2 and 30 micrometers.

"The fabrication method of the metal layer and the conductive layer can comprise: forming a resist layer on the metal board and forming a plurality of openings in the resist layer to expose a portion of the metal board; forming the metal layer on the metal board in the openings of the resist layer; forming the conductive layer on the metal layer in the openings of the resist layer; and removing the resist layer to expose the metal board and the metal layer and the conductive layer on the metal board.

"In the above-described semiconductor package and fabrication method thereof, the size of the trace ends can be greater than that of the openings of the solder mask layer. The trace ends can be, but not limited to, of an elliptical shape, a circular shape or a cruciform shape. The conductive layer can be made of one or more materials selected from the group consisting of Au, Pd and Ni. The conductive layer can further comprise power pads and ground pads electrically connecting to the bonding wires.

"In an embodiment, the trace ends can be partially exposed from the openings of the solder mask layer, respectively, and a portion of the encapsulant can be exposed from the openings of the solder mask layer. Further, a portion of the surface of the die pad can be exposed from the openings of the solder mask layer.

"The present invention further provides another semiconductor package having electrical connecting structures, which comprises: a conductive layer with a plurality of traces, each of the traces having a trace body, a contact pad formed at one end of the trace body and positioned proximate to a chip, and a trace end formed at the other end of the trace body and positioned distal to the chip; the chip flip-chip connected to the contact pads; an encapsulant encapsulating the chip and the conductive layer, wherein the encapsulant has a plurality of cavities with a depth greater than the thickness of the conductive layer for embedding the conductive layer therein, the cavities allowing at least a portion of the surface of the conductive layer to be exposed therefrom; a solder mask layer formed on the exposed surface of the conductive layer and a bottom surface of the encapsulant and having a plurality of openings for exposing the trace ends; and a plurality of solder balls formed in the openings of the solder mask layer so as to electrically connect to the trace ends, respectively.

"In the semiconductor package, the difference between the depth of the cavities and the thickness of the conductive layer is in the range of 2 and 30 micrometers.

"The present invention further provides a fabrication method of a semiconductor package having electrical connecting structures, which comprises: providing a metal board with a plurality of substrate units; forming a patterned metal layer on the substrate units; forming a conductive layer on the metal layer, wherein the conductive layer has a plurality of traces each comprising a trace body, a contact pad positioned proximate to one end of the trace body, and a trace end formed at the other end of the trace body and opposite to the contact pad; mounting a chip in a flip-chip manner so as to electrically connect the chip to the contact pads; forming an encapsulant to cover the chip and the conductive layer; removing the metal board and the metal layer so as to expose the conductive layer, wherein the encapsulant has a plurality of cavities with a depth greater than the thickness of the conductive layer for embedding the traces of the conductive layer therein; forming a solder mask layer on the exposed surface of the conductive layer and the bottom surface of the encapsulant, and forming a plurality of openings in the solder mask layer to expose the trace ends; forming a plurality of solder balls in the openings of the solder mask layer, respectively; and singulating the substrate units from each other so as to obtain a plurality of semiconductor packages.

"In the above fabrication method, the metal board can be made of copper; the metal layer can be made of one or more materials selected from the group consisting of Ni, Sn and Pb; and the metal layer can have a thickness between 2 and 30 micrometers.

"The fabrication method of the metal layer and the conductive layer comprises: forming a resist layer on the metal board and forming a plurality of openings in the resist layer to expose a portion of the metal board; forming the metal layer on the metal board in the openings of the resist layer; forming the conductive layer on the metal layer in the openings of the resist layer; and removing the resist layer to expose the metal board and the metal layer and the conductive layer on the metal board.

"In the above semiconductor package and fabrication method thereof, the conductive layer can be made of one or more materials selected from the group consisting of Au, Pd and Ni; the size of the trace ends can be greater than that of the openings of the solder mask layer; the trace ends can have an elliptical shape, a circular shape or a cruciform shape; the trace ends can be partially exposed from the openings of the solder mask layer, respectively, and a portion of the encapsulant can be exposed from the openings of the solder mask layer.

"According to the present invention, the traces extend towards the die pad so as to reduce the length of the bonding wires. Since the cavities of the encapsulant have a depth greater than the thickness of the die pad and the traces of the conductive layer, the solder mask layer and the encapsulant can be engaged with each other for enhancing the adhesion strength of the solder mask layer. Meanwhile, the solder mask layer can prevent solder bridging from occurring during a thermal process. Further, the cavities of the encapsulant having a depth greater than the thickness of the die pad and the traces of the conductive layer allow the die pad and the traces to be embedded therein, thereby protecting the conductive layer from scratching. Furthermore, the bonding between the solder mask layer and the encaspulant as well as the conductive layer in such as a horizontal direction and a vertical direction, prolong the permeation path of solder material or moisture into the package. As such, electrical leakage caused by delamination of the solder mask layer, moisture permeating into the package, and short circuit caused by permeation of solder material in the prior art, can be prevented."

For more information, see this patent: Lin, Pang-Chun; Li, Chun-Yuan; Tang, Fu-Di; Huang, Chien-Ping; Ke, Chun-Chi. Semiconductor Package Having Electrical Connecting Structures and Fabrication Method. U.S. Patent Number 8716861, filed February 27, 2013, and published online on May 6, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=73&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=3612&f=G&l=50&co1=AND&d=PTXT&s1=20140506.PD.&OS=ISD/20140506&RS=ISD/20140506

Keywords for this news article include: Electronics, Circuit Board, Semiconductor, Siliconware Precision Industries Co. Ltd.

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Source: Electronics Newsweekly


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