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Patent Issued for Reconfigurable Multi-Level Sensing Scheme for Semiconductor Memories

May 21, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventors Lam, Chung H. (Peekskill, NY); Lewis, Scott C. (Essex Junction, VT); Li, Jing (Ossining, NY), filed on September 12, 2011, was published online on May 6, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8717802 is assigned to International Business Machines Corporation (Armonk, NY).

The following quote was obtained by the news editors from the background information supplied by the inventors: "Typical semiconductor memories are fabricated on semiconductor substrates including arrays of a large number of physical memory cells. In general, one bit of binary data is represented as a variation of a physical parameter associated with a memory cell. Commonly used physical parameters may include, for example, threshold voltage variation of a metal-oxide-semiconductor field effect transistor (MOSFET) in a memory cell of the memory device due to the amount of charge stored in a floating gate or a trap layer in non-volatile electrically erasable programmable read-only memory (EEPROM), resistance variation of a phase change memory (PCM) element in phase-change random access memory (PCRAM) or ovonic unified memory (OUM), and charge storage variation in volatile dynamic random access memory (DRAM).

"Some issued U.S. patents which may be relevant to an understanding of the invention by the skilled artisan include, but are not limited to, U.S. Pat. No. 7,567,473 entitled 'Multi-level Memory Cell Utilizing Measurement Time Delay as the Characteristic Parameter for Level Definition,' U.S. Pat. No. 7,602,631 entitled 'Multi-level Memory Cell Utilizing Measurement Time Delay as the Characteristic Parameter for Level Definition,' U.S. Pat. No. 7,602,632 entitled 'Multi-level Memory Cell Utilizing Measurement Time Delay as the Characteristic Parameter for Level Definition,' U.S. Pat. No. 7,480,184 entitled 'Maximum Likelihood Statistical Method of Operations for Multi-bit Semiconductor Memory,' U.S. Pat. No. 5,936,906 entitled 'Multilevel Sense Device for Flash Memory,' U.S. Pat. No. 6,009,040 entitled 'Apparatus and Methods for Controlling Sensing Time in a Memory Device,' U.S. Pat. No. 6,307,783 entitled 'Descending Staircase Read Technique for a Multilevel Cell NAND Flash Memory Device,' U.S. Pat. No. 6,956,779 entitled 'Multistage Autozero Sensing for a Multilevel Non-volatile Memory Integrated Circuit System,' U.S. Pat. No. 6,961,266 entitled 'Method of Programming-Reading Multi-Level Flash Memory Using Sensing Circuit,' U.S. Pat. No. 6,975,539 entitled 'Digital Multilevel Non-volatile Memory System,' U.S. Pat. No. 7,142,464 entitled 'Apparatus and Methods for Multi-level Sensing in a Memory Array,' U.S. Pat. No. 7,532,529 entitled 'Apparatus and Methods for Multi-level Sensing in a Memory Array,' U.S. Pat. No. 7,359,246 entitled 'Memory Device with a Ramp-Like Voltage Biasing Structure Base on a Current Generator,' and U.S. Pat. No. 7,580,297 entitled 'Readout of Multi-Level Storage Cells,' the respective disclosures of which are incorporated herein by reference in their entireties for all purposes.

"Multi-level cell (MLC) memory architectures having the capability of storing more than one bit of binary information in a given memory cell are well known. However, conventional sensing schemes for reading the respective states of MLCs in a memory array are often complex, slow, and inflexible, among other disadvantages, and thus undesirable."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "The present invention, in illustrative embodiments thereof, relates to techniques for sensing the respective states of a MLC memory cell. Compared to conventional sensing schemes used, for example, in MLC flash memory architectures, sensing techniques according to aspects of the invention offer benefits of a simple structure, smaller chip area, faster speed (compared to MLC flash memory), increased fault tolerance, and flexibility in changing a precision level of the sensing operation for adapting, on the fly, to the number of bits stored in the memory cells, among other advantages.

"In accordance with an embodiment of the invention, a method for sensing at least one parameter indicative of a logical state of a multi-level memory cell includes the steps of: measuring the parameter of the multi-level memory cell; comparing the measured parameter of the multi-level memory cell with a prescribed reference signal, the reference signal having a value which varies as a function of time; and storing a time value corresponding to a point in time at which the reference signal is substantially equal to the measured parameter of the multi-level memory cell, the stored time value being indicative of a sensed logical state of the multi-level memory cell.

"In accordance with another embodiment of the invention, a sense circuit for sensing at least one parameter indicative of a state of a multi-level memory cell includes a reference signal generator operative to generate a reference signal having a value which dynamically varies as a function of time. The sense circuit further includes a monitor circuit operative to measure the parameter of the multi-level memory cell and to generate a sensed parameter signal indicative of a state of the multi-level memory cell. A comparator in the sense circuit is operative to receive the reference signal and the sensed parameter signal and to generate an output signal as a function of a difference between the reference signal and the sensed parameter signal. The sense circuit further includes memory operative as a function of the output signal generated by the comparator to store a time value corresponding to a point in time at which the reference signal is substantially equal to the sensed parameter signal. The stored time value is indicative of a sensed logical state of the multi-level memory cell.

"These and other features, objects and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings."

URL and more information on this patent, see: Lam, Chung H.; Lewis, Scott C.; Li, Jing. Reconfigurable Multi-Level Sensing Scheme for Semiconductor Memories. U.S. Patent Number 8717802, filed September 12, 2011, and published online on May 6, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=54&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=2675&f=G&l=50&co1=AND&d=PTXT&s1=20140506.PD.&OS=ISD/20140506&RS=ISD/20140506

Keywords for this news article include: Electronics, Legal Issues, Semiconductor, Random Access Memory, International Business Machines Corporation.

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Source: Electronics Newsweekly


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