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Patent Issued for Nonvolatile Memory Devices, Memory Systems and Methods of Performing Read Operations

May 21, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- Samsung Electronics Co., Ltd. (Suwon-si, Gyeonggi-do, KR) has been issued patent number 8717832, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventor is Kim, Seung-Bum (Hwaseong-si, KR).

This patent was filed on October 8, 2013 and was published online on May 6, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "The present disclosure is related to methods of operating nonvolatile memory devices, nonvolatile memory devices and systems incorporating same. More particularly, the disclosure relates to methods of adjusting the nature and timing of control signals applied to nonvolatile memory cell(s) during various read operations.

"Nonvolatile memory devices and memory systems incorporating same have become design mainstays within contemporary electronic devices and digital data systems. There are many different types of nonvolatile memory, including the Electrically Erasable Programmable Read Only Memory (EEPROM). So-called 'flash memory' is one type of EEPROM and is widely used since it is not only allows random programmability like a Random Access Memory (RAM), but also the ability to retain stored data in the absence of applied power like a Read Only Memory (ROM). As a result of these qualities, flash memory is now widely used as data storage media, particularly in portable electronic devices such as laptop and notepad computers, digital cameras, personal digital assistants (PDAs), and MP3 players."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventor's summary information for this patent: "Certain embodiments of the inventive concept provide a method of operating a non-volatile memory device, comprising; during a read operation directed to a nonvolatile memory cell having a positive threshold voltage and being connected between a selected word line and a selected bit line, applying a positive read voltage to the selected word line and a first control signal to a page buffer connected to the selected bit line, and during a read operation directed to the memory cell having a negative threshold voltage, applying a negative read voltage to the selected word line and a second control signal to the page buffer different from the first control signal.

"In a related aspect, the second control signal causes relatively more electrical charge to be accumulated or retained on the selected bit line than the first control signal.

"In another related aspect, the first control signal defines a first read operation interval comprising a first discharge interval, a first pre-charge interval, a first developing interval, and a first sensing interval, and the second control signal defines a second read operation interval comprising a second discharge interval, a second pre-charge interval, a second developing interval, and a second sensing interval.

"In another related aspect, the second read operation interval is longer in duration than the first read operation interval.

"In another related aspect, the second pre-charge interval is longer in duration than the first pre-charge interval.

"In another related aspect, the second read operation interval is longer in duration than the first read operation interval.

"In another related aspect, the second pre-charge interval begins relatively sooner in the second read operation interval than the first pre-charge interval begins in the first read operation interval.

"In another related aspect, the second developing interval begins relatively later in the second read operation interval than the first developing interval begins in the first read operation interval.

"In another related aspect, application of the positive read voltage and application of the negative read voltage to the selected word line are symmetrical over at least a portion of the read operation interval and with respect to an initial word line voltage.

"In another related aspect, application of the positive read voltage and application of the negative read voltage to the selected word line are asymmetrical over a at least a portion of the read operation interval and with respect to an initial word line voltage.

"In another related aspect, the negative read voltage is applied to the selected word line over a longer portion of the read operation interval than the positive read voltage.

"In another related aspect, the negative read voltage is applied to the selected word line in relation to a negative target voltage with a different voltage slope characteristic than the positive read voltage is applied to the selected word line in relation to a positive target voltage.

"In another related aspect, a voltage slope characteristic for the negative read voltage is steeper towards the negative target voltage than a voltage slope characteristic for the positive read voltage is towards the positive target voltage.

"In another related aspect, an absolute value of a positive difference between the initial word line voltage and a positive target voltage associated with the positive read voltage is less than an absolute value of a negative difference between the initial word line voltage and a negative target voltage associated with the negative read voltage.

"In another related aspect, the read operation is a program-read-verify operation, or an erase-read-verify operation.

"In another related aspect, the nonvolatile memory cell is a multi-level memory cell (MLC).

"In another related aspect, the nonvolatile memory cell is a NAND type flash memory cell.

"In another embodiment, the inventive concept provides a method of operating a non-volatile memory device, comprising; during a read operation directed to a memory cell connected between a selected word line and a selected bit line and applying a positive read voltage to the selected word line, applying a bit line voltage to the selected bit line at a first time relative to a time at which the positive read voltage is applied to the selected word line, and during a read operation directed to the memory cell and applying a negative read voltage to the selected word line, applying the bit line voltage to the selected bit line at a second time later than the first time, such that application of the bit line voltage occurs during an interval wherein the negative read voltage is transitioning from an initial word line voltage to a negative target voltage.

"In another related aspect, the memory cell has a threshold voltage between the negative target voltage and the negative read voltage such that an ON period for the memory cell following application of the negative read voltage is reduced.

"In yet another embodiment, the inventive concept provides a method of reading data stored in a non-volatile memory cell according to a defined threshold voltage distribution, the memory cell being connected between a selected word line and a selected bit line and the method comprising; determining whether the threshold voltage distribution is positive or negative, if the threshold voltage distribution is positive, applying a positive read voltage to the selected word line during a first read operation interval including a first discharge interval, a first pre-charge interval, a first developing interval, and a first sensing interval, and if the threshold voltage is negative, applying a negative read voltage to the selected word line during a second read operation interval different from the first read operation interval and including a second discharge interval, a second pre-charge interval, a second developing interval, and a second sensing interval.

"In another related aspect, the second pre-charge interval is longer than the first pre-charge interval.

"In another related aspect, the method further comprises; generating a first control signal defining the first read operation interval if the threshold voltage distribution is positive, and generating a second control signal defining the second read operation interval if the threshold voltage distribution is negative.

"In yet another embodiment, the inventive concept provides a nonvolatile memory device comprising; a nonvolatile memory cell, and operation control circuitry comprising control logic configured to apply either a positive read voltage or a negative read voltage to a selected word line connected to the nonvolatile memory cell, and further configured to adjust timing of a read operation interval for a read operation determining a data state for the nonvolatile memory cell based on whether the positive read voltage or the negative read voltage is applied to the selected word line.

"In a related aspect, the read operation is a program-read-verify operation of an erase-read-verify operation.

"In another related aspect, the control logic is further configured to control generation of either the positive read voltage or negative read voltage, and generation of either a first control signal defining a first read operation interval during which the positive read voltage is applied to the selected word line or a second control signal defining a second read operation interval during which the negative read voltage is applied to the selected word line.

"In another related aspect, the first and second read operation intervals respective comprise a discharge interval, a pre-charge interval, a developing interval, and a sensing interval.

"In another related aspect, the second read operation interval is longer in duration than the first read operation interval.

"In another related aspect, the pre-charge interval of the second read operation interval is longer in duration than a pre-charge interval of the first read operation interval.

"In another related aspect, the operation control circuitry comprises; a voltage generator configured to generate the positive read voltage and the negative read voltage under the control of the control logic, and a page register and sense amplifier block configured to define the first read operation interval in response to the first control signal and the second read operation interval in response to the second control signal.

"In another embodiment, the invention provides a nonvolatile memory device comprising; a nonvolatile memory cell, and operation control circuitry configured to apply a positive read voltage to a selected word line connected to the nonvolatile memory cell if the nonvolatile memory cell has a positive threshold voltage, and apply a negative read voltage to the selected word line if the nonvolatile memory cell has a negative threshold voltage, wherein the positive read voltage and negative read voltage are applied asymmetrical over a portion of a read operation interval and with respect to an initial word line voltage of the selected word line.

"In a related aspect, the negative read voltage is applied to the selected word line over a longer portion of the read operation interval than the positive read voltage.

"In another related aspect, the negative read voltage is applied to the selected word line in relation to a negative target voltage with a different voltage slope characteristic than the positive read voltage applied to the selected word line in relation to a positive target voltage.

"In another embodiment, the invention provides a memory card comprising; a card interface, and a controller configured to control an exchange of data between the card interface and the nonvolatile memory device as described above.

"In another embodiment, the invention provides a memory system comprising; the nonvolatile memory device described above and a controller configured to control operation of the nonvolatile memory device. In one aspect, the nonvolatile memory device and controller may be configured to collectively operate as a solid state drive (SSD)."

For the URL and additional information on this patent, see: Kim, Seung-Bum. Nonvolatile Memory Devices, Memory Systems and Methods of Performing Read Operations. U.S. Patent Number 8717832, filed October 8, 2013, and published online on May 6, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=53&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=2645&f=G&l=50&co1=AND&d=PTXT&s1=20140506.PD.&OS=ISD/20140506&RS=ISD/20140506

Keywords for this news article include: Samsung Electronics Co. Ltd.

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Source: Electronics Newsweekly


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