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Patent Issued for Liquid Crystal Display Device and Manufacturing Method

May 21, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventors Nitta, Hidekazu (Chiba, JP); Miyake, Hidekazu (Mobara, JP); Kaitoh, Takuo (Mobara, JP), filed on October 4, 2011, was published online on May 6, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8717510 is assigned to Hitachi Displays, Ltd. (Chiba, JP).

The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention relates to a liquid crystal display device. More particularly, the invention relates to a liquid crystal display device in which a thin film transistor has a high ON-current for pixel control, quick writing of video signals are achieved, and there is less variation in ON-current characteristics.

"A liquid crystal panel for use in a liquid crystal display device includes a TFT substrate having pixel electrodes, thin film transistors (TFT), or the like formed thereon in a matrix form, and a counter electrode opposing the TFT substrate and having color filters, or the like formed at positions corresponding to the pixel electrodes of the TFT substrate. Liquid crystals are put between the TFT substrate and the counter substrate. The liquid crystal display device controls light transmittance for each pixel by using liquid crystal molecules to form images.

"The number of pixels has increased in the screen of the liquid crystal device due to enlargement in the size thereof and high definition. Since, in such a case, the frequency at which video signals are written in one frame increases, the time it takes for writing video signals to each pixel is restricted. For enabling short-time writing to each pixel, the ON-current of a TFT in the pixel needs to be increased while the OFF-current of the TFT needs to be kept small.

"To address the problems as described above, JP-A-11-17188 describes a configuration in which a contact portion between a semiconductor layer formed of a-Si that operates as an active layer of a TFT and a drain electrode or a source electrode is formed by two layers of a n.sup.+-a-Si layer and a n.sup.+-poly-Si (microcrystalline silicon) layer."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "In the technique described in JP-A-11-17188, different kinds of semiconductors such as the n.sup.+-a-Si layer and the n.sup.+-poly-Si layer have to be formed between a semiconductor layer 103 and a drain electrode 107 or a source electrode 108. Thus the relevant process is difficult to control.

"As a technique for increasing the ON-current of the TFT, a technique has been developed for forming a n.sup.+-a-Si layer not only on the upper surface a semiconductor layer 103 but also on the side of the semiconductor layer 103. The semiconductor 103 comprises an a-Si layer. Such a configuration, which is shown in FIG. 10, is referred to as a side wall TFT.

"A liquid crystal display device is formed by putting a liquid crystal layer between a TFT substrate 100 and a counter substrate. FIG. 10 is a cross sectional view of the TFT substrate 100. For the TFT substrate 100 shown in FIG. 10, an alignment film is not shown.

"In FIG. 10, a n.sup.+-a-Si layer covers the upper surface and the side of a semiconductor layer 103. Since, in such a structure, the ON-current of a TFT can flow also on the side of the semiconductor layer 103, the ON-current can be increased. In contrast, the OFF-current of the TFT can be kept at an existent level.

"A process for forming the TFT substrate 100 shown in FIG. 10 is to be shown with reference to FIG. 11 to FIG. 16. Referring to FIG. 11, a gate electrode 101 is formed on a TFT substrate 100 formed of glass, a gate insulating film 102 is formed to cover a gate electrode 101, and a semiconductor layer 103 comprising a-Si is formed on a gate insulating film 102 and over the gate electrode 101. Successively, the semiconductor layer 103 is patterned as shown in FIG. 12.

"Subsequently, as shown in FIG. 13, a n.sup.+-a-Si layer is formed to cover the semiconductor layer 103 and the gate insulating film 102. n.sup.+-a-Si serves to provide ohmic contact between a drain electrode 107 and a source electrode 108 which are subsequent formed of a metal and semiconductor layer 103. The n.sup.+-a-Si layer covers not only the upper surface of semiconductor layer 103 but also the side of the semiconductor layer 103. This intends to increase the ON-current.

"Then, as shown in FIG. 14, a metal layer 106 comprising, for example, MoCr is formed to cover the n.sup.+-a-Si layer for forming the drain electrode 107 and the source electrode 108. Successively, as shown in FIG. 15, the metal layer 106 is patterned by photolithography to form the drain electrode 107 and the source electrode 108.

"Then, as shown in FIG. 15, the n.sup.+-a-Si layer is dry etched by using the drain electrode 107 and the source electrode 108 as a resist thereby patterning the n.sup.+-a-Si layer. In this step, the characteristic of a channel region is stabilized by etching also a portion of the semiconductor layer 103 at a region where the drain electrode 107 and the source electrode 108 are opposed. A removed region of the semiconductor layer is referred to as a channel etching 120.

"Then, a passivation film 109 is coated over the entire TFT substrate 100 including a TFT. This is for protecting the TFT. A through hole 110 is formed in the passivation film 109 for connecting a pixel electrode 111 formed subsequently to the source electrode 108 of the TFT. Then, ITO (Indium Tin Oxide) as a transparent conductive film to form the pixel electrode 111 is deposited and ITO is patterned to form the pixel electrode 111.

"The side wall TFT descried above involves a problem that the ON-current varies. This is considered to be the following phenomenon. The semiconductor layer 103 in FIG. 12 and the n.sup.+-a-Si layer in FIG. 13 are formed by plasma CVD. The plasma CVD is generated in one identical chamber.

"The semiconductor layer 103 comprising a-Si is an i-type semiconductor. Since the characteristic of the semiconductor layer 103 fluctuates sensitively by an impurity, the inside of a chamber for plasma CVD is made clean by coating an insulator such as of SiN in the chamber before deposition of the semiconductor layer 103. That is, by covering the inside of the chamber with the insulator, intrusion of an impurity deposited on the wall of the chamber, etc. into the semiconductor layer 103 is prevented.

"The coating operation described above is performed every time the semiconductor 103 is formed. That is, when the semiconductor 103 is deposited to one substrate, vacuum in the chamber is released and the substrate is taken out. An insulator is coated to the chamber to clean the inside of the chamber before plasma CVD is conducted in the chamber for other substrate.

"Then, the amount of the laminate of the insulator film and the a-Si film is increased more for substrates processed later. Accordingly, the condition for forming the semiconductor layer 103 to the first substrate is different from that for forming the semiconductor layer 103 to the last substrate. Actually, this results in a phenomenon that the ON-current of the TFT varies on every substrate.

"That is, in the past, while the ON-current of the TFT was large in a substrate over which the semiconductor layer 103 is first formed by plasma CVD, the ON-current was decreased for the substrates processed later. Such variation of the TFT characteristics is not desirable as characteristics for the entire liquid crystal display device.

"On the other hand, when a thick insulator is coated in the chamber before plasma CVD processing, the ON-current of the formed TFT is decreased. However, the difference of the ON-current of the TFT depending on the processing order is decreased between each of the substrates undergoing the plasma CVD.

"That is, both the substrate initially put to the plasma CVD and the substrate finally put to the plasma CVD are stabilized at a small ON-current. In the past, the insulator film was coated thickly in the chamber from the beginning for suppressing the variation of the ON-current. Accordingly, TFTs of small ON-current had to be used.

"However, as the screen is enlarged in the size or increased in definition, the number of pixels is increased to result in restriction for the time of writing video signals. For making the writing of the video signal at a higher speed, it is necessary to increase the ON-current of the TFT. The present invention intends to increase the ON-current of a TFT, as well as suppress variation of the ON-current.

"The present invention intends to solve the subject described above and specific means therefor is as described below. That is, after a semiconductor layer comprising a-Si is formed, a first n.sup.+-a-Si layer is formed thinly in one identical chamber continuously without breaking vacuum. The semiconductor layer is formed by plasma CVD in a phosphine atmosphere and the n.sup.+-a-Si layer is formed by plasma CVD in a phosphorus (P)-doped phosphine atmosphere.

"The ON-current of the TFT is increased by the diffusion of phosphorus (P) doped in n.sup.+-a-Si into the semiconductor layer. On the other hand, the OFF-current is kept low as it is. In such a process, the amount of phosphorus (P) upon forming the first n.sup.+-a-Si layer can be controlled intentionally. Accordingly, the ON-current of the TFT can be increased and, at the same time, variation can be suppressed.

"Subsequently, a substrate having a semiconductor layer and n.sup.+-a-Si stacked thereover is taken out of the chamber and patterned by etching. Then, a second n.sup.+-a-Si layer is formed by plasma CVD in a phosphorus (P)-doped phosphine atmosphere. The second n.sup.+-a-Si layer forms a side wall covering the side of the semiconductor layer to increase the ON-current. The subsequent process is identical with the usual process.

"That is, according to the invention, a first n.sup.+-a-Si layer formed contiguous with and over the semiconductor layer and patterned at the same time, and a second n.sup.+-a-Si layer forming the side wall for increasing the ON-current are formed between the drain electrode and the source electrode.

"According to the invention, since the semiconductor layer and the n.sup.+-a-Si layer are formed continuously by plasma CVD in one identical chamber, the ON-current characteristics of the semiconductor layer can be controlled stably. That is, the ON-current of the TFT can be maintained high while the variation thereof is restricted. Further, the OFF-current of the TFT can be kept low as usual.

"Thus, the time for writing video signals can be shortened and, even when the number of pixels is increased due to enlargement in the size and increase in the definition of the screen, since signals can be written at high speed, image reproducibility can be maintained and display at high image quality can be attained."

URL and more information on this patent, see: Nitta, Hidekazu; Miyake, Hidekazu; Kaitoh, Takuo. Liquid Crystal Display Device and Manufacturing Method. U.S. Patent Number 8717510, filed October 4, 2011, and published online on May 6, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=60&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=2966&f=G&l=50&co1=AND&d=PTXT&s1=20140506.PD.&OS=ISD/20140506&RS=ISD/20140506

Keywords for this news article include: Electronics, Hitachi Displays, Hitachi Displays Ltd., Organophosphorus Compounds, Phosphines, Phosphorus Compounds, Semiconductor.

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Source: Electronics Newsweekly


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